On the assessment of voids in the thermal interface material on the thermal performance of a silicon chip package

The current investigation assesses the effect of voids in the thermal interface material (TIM) on the thermal performance of silicon chip packages. The effects of the voids were included in the TIM using a series of analytical and numerical models that employed an effective volume-averaged thermal conductivity for the TIM and the actual voids within the TIM. Different void concentrations and distributions were evaluated using this numerical simulation process. The junction-to-air thermal resistance of the package was calculated in order to effectively evaluate the thermal performance of the chip package. A series of parametric studies were conducted and indicated that a 3-D numerical model using actual holes up to a number of 100 and at different concentrations in volume predicts similar results as a 3-D model using a volume-average effective thermal conductivity of the TIM. Finally, it was found that the analytical model developed here provides results that compare favorably with those obtained using more complex and time intensive 3-D models (approximately 7-10%).