On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package

M. Lee; J. Kim; A. Singh; H. M. Torun; M. Swaminathan; S. Lim; S. Mukhopadhyay

doi:10.1109/S3S.2018.8640215

On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package

M. Lee, J. Kim, A. Singh, H. M. Torun, M. Swaminathan, S. Lim, S. Mukhopadhyay

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Interposer-based 2.5D System-in-Package (SiP) allows heterogeneous integration while promising lower cost and higher yield than TSV-based 3D integration [1] [2] [3]. Communications between dies in SiP are similar to those in System-on-Chip (SoC), except SiP is using wires in silicon interposers which have larger linewidth and show inductive properties. The total number of input/output (I/O) circuits to drive on-interposer wires is much larger than off-chip I/Os in SoC. Hence, design of lightweight I/O circuits is critical for 2.5D integrations, and digital singled-ended signaling has emerged as a preferred choice.

Original language	English (US)
Title of host publication	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Publisher	Institute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)	9781538676264
DOIs	https://doi.org/10.1109/S3S.2018.8640215
State	Published - Jul 2 2018
Event	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 - Burlingame, United States Duration: Oct 15 2018 → Oct 18 2018

Publication series

Name	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018

Conference

Conference	2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018
Country/Territory	United States
City	Burlingame
Period	10/15/18 → 10/18/18

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering
Safety, Risk, Reliability and Quality
Electronic, Optical and Magnetic Materials
Instrumentation

Access to Document

10.1109/S3S.2018.8640215

Cite this

Lee, M., Kim, J., Singh, A., Torun, H. M., Swaminathan, M., Lim, S., & Mukhopadhyay, S. (2018). On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 Article 8640215 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/S3S.2018.8640215

Lee, M. ; Kim, J. ; Singh, A. et al. / On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package. 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2018. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

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title = "On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package",

abstract = "Interposer-based 2.5D System-in-Package (SiP) allows heterogeneous integration while promising lower cost and higher yield than TSV-based 3D integration [1] [2] [3]. Communications between dies in SiP are similar to those in System-on-Chip (SoC), except SiP is using wires in silicon interposers which have larger linewidth and show inductive properties. The total number of input/output (I/O) circuits to drive on-interposer wires is much larger than off-chip I/Os in SoC. Hence, design of lightweight I/O circuits is critical for 2.5D integrations, and digital singled-ended signaling has emerged as a preferred choice.",

author = "M. Lee and J. Kim and A. Singh and Torun, {H. M.} and M. Swaminathan and S. Lim and S. Mukhopadhyay",

note = "Funding Information: ACKNOWLEDGEMENT: This research is funded by DARPA CHIPS project under Award N00014-17-1-2950. Publisher Copyright: {\textcopyright} 2018 IEEE.; 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018 ; Conference date: 15-10-2018 Through 18-10-2018",

year = "2018",

month = jul,

day = "2",

doi = "10.1109/S3S.2018.8640215",

language = "English (US)",

series = "2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018",

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Lee, M, Kim, J, Singh, A, Torun, HM, Swaminathan, M, Lim, S & Mukhopadhyay, S 2018, On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package. in 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018., 8640215, 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Institute of Electrical and Electronics Engineers Inc., 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018, Burlingame, United States, 10/15/18. https://doi.org/10.1109/S3S.2018.8640215

On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package. / Lee, M.; Kim, J.; Singh, A. et al.
2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc., 2018. 8640215 (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Lee, M.

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AU - Singh, A.

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AU - Lim, S.

AU - Mukhopadhyay, S.

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N2 - Interposer-based 2.5D System-in-Package (SiP) allows heterogeneous integration while promising lower cost and higher yield than TSV-based 3D integration [1] [2] [3]. Communications between dies in SiP are similar to those in System-on-Chip (SoC), except SiP is using wires in silicon interposers which have larger linewidth and show inductive properties. The total number of input/output (I/O) circuits to drive on-interposer wires is much larger than off-chip I/Os in SoC. Hence, design of lightweight I/O circuits is critical for 2.5D integrations, and digital singled-ended signaling has emerged as a preferred choice.

AB - Interposer-based 2.5D System-in-Package (SiP) allows heterogeneous integration while promising lower cost and higher yield than TSV-based 3D integration [1] [2] [3]. Communications between dies in SiP are similar to those in System-on-Chip (SoC), except SiP is using wires in silicon interposers which have larger linewidth and show inductive properties. The total number of input/output (I/O) circuits to drive on-interposer wires is much larger than off-chip I/Os in SoC. Hence, design of lightweight I/O circuits is critical for 2.5D integrations, and digital singled-ended signaling has emerged as a preferred choice.

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Lee M, Kim J, Singh A, Torun HM, Swaminathan M, Lim S et al. On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package. In 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018. Institute of Electrical and Electronics Engineers Inc. 2018. 8640215. (2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018). doi: 10.1109/S3S.2018.8640215

On the design of energy-efficient I/O circuits for interposer-based 2.5D system-in-package

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All Science Journal Classification (ASJC) codes

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