On the effects of process variation in network-on-chip architectures

Keyphrases

• Process Variation 100%
• Network-on-chip Architectures 100%
• Network on chip 50%
• Electrical Properties 25%
• Overall System Performance 25%
• Performance Improvement 25%
• Comprehensive Evaluation 25%
• Router 25%
• Power Efficiency 25%
• Viable Solutions 25%
• Gate Delay 25%
• Area-efficient 25%
• Transistor Count 25%
• Technology Process 25%
• Process Variation Effect 25%
• Transistor Density 25%
• Global Interconnect 25%
• Interconnect Delay 25%
• Diminutive 25%
• Technology Features 25%
• Deep Submicron Technology 25%
• Chip Design 25%
• On-chip Router 25%

Engineering

• Process Variation 100%
• Network-on-Chip 100%
• Chip Architecture 100%
• Systems Performance 20%
• Feature Size 20%
• Interconnects 20%
• Manufacturing Imperfection 20%

Computer Science

• Networks on Chips 100%
• Process Variation 100%
• Chip Architecture 100%
• Systems Performance 20%
• Critical Component 20%
• Power Efficiency 20%
• Interconnect Delay 20%