Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the micro-architectural impact of using multiple PLLs for clock distribution. Two PLL phase synchronization algorithms are presented and analyzed They are compared in terms of efficiency performance, and complexity. For both, the micro-architectural impact is small, but certainly not negligible.
|Original language||English (US)|
|Number of pages||7|
|Journal||Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors|
|State||Published - 2001|
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering