On the micro-architectural impact of clock distribution using multiple PLLs

Martin Saint-Laurent; Madhavan Swaminathant; James D. Meindl

doi:10.1109/ICCD.2001.955031

On the micro-architectural impact of clock distribution using multiple PLLs

Martin Saint-Laurent, Madhavan Swaminathant, James D. Meindl

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

13 Scopus citations

Abstract

Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the micro-architectural impact of using multiple PLLs for clock distribution. Two PLL phase synchronization algorithms are presented and analyzed They are compared in terms of efficiency performance, and complexity. For both, the micro-architectural impact is small, but certainly not negligible.

Original language	English (US)
Article number	33
Pages (from-to)	214-220
Number of pages	7
Journal	Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
DOIs	https://doi.org/10.1109/ICCD.2001.955031
State	Published - 2001

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

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10.1109/ICCD.2001.955031

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abstract = "Clock distribution has traditionally been a circuit design problem with negligible micro-architectural impact. However, for clock distribution networks using multiple phase-locked loops (PLLs), this will most likely not be the case. This paper discusses the micro-architectural impact of using multiple PLLs for clock distribution. Two PLL phase synchronization algorithms are presented and analyzed They are compared in terms of efficiency performance, and complexity. For both, the micro-architectural impact is small, but certainly not negligible.",

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On the micro-architectural impact of clock distribution using multiple PLLs

Abstract

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