On the parasitic gate capacitance of small-geometry MOSFETs

Mamidala Jagadesh Kumar; Vivek Venkataraman; Sumeet Kumar Gupta

doi:10.1109/TED.2005.850630

On the parasitic gate capacitance of small-geometry MOSFETs

Mamidala Jagadesh Kumar, Vivek Venkataraman, Sumeet Kumar Gupta

Electrical Engineering

Research output: Contribution to journal › Article › peer-review

7 Scopus citations

Abstract

In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for C_top and C_bottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.

Original language	English (US)
Pages (from-to)	1676-1677
Number of pages	2
Journal	IEEE Transactions on Electron Devices
Volume	52
Issue number	7
DOIs	https://doi.org/10.1109/TED.2005.850630
State	Published - Jul 2005

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

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10.1109/TED.2005.850630

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title = "On the parasitic gate capacitance of small-geometry MOSFETs",

abstract = "In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for Ctop and Cbottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.",

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AU - Kumar, Mamidala Jagadesh

AU - Venkataraman, Vivek

AU - Gupta, Sumeet Kumar

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Y1 - 2005/7

N2 - In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for Ctop and Cbottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.

AB - In most cases, accurate and simple models are required to predict the detrimental effect of the parasitic capacitances in aggressively scaled-down MOSFETs. Correct models for Ctop and Cbottom should be employed since each of these capacitances, if considered independently, will have a different effect on the device performance.

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U2 - 10.1109/TED.2005.850630

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M3 - Article

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EP - 1677

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

IS - 7

ER -

On the parasitic gate capacitance of small-geometry MOSFETs

Abstract

All Science Journal Classification (ASJC) codes

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