TY - JOUR
T1 - Optimal clock distribution with an array of phase-locked loops for multiprocessor chips
AU - Saint-Laurent, Martin
AU - Zarkesh-Ha, Payman
AU - Swaminathan, Madhavan
AU - Meindl, James D.
PY - 2001
Y1 - 2001
N2 - This paper discusses clock distribution for chips with multiple microprocessor cores. A model for clock distribution with an array of phase-locked loops (PLLs) is introduced. The model is used to derive an analytical expression describing the optimal design tradeoff between power dissipation and clock inaccuracy. With parameters typical for a 180-nm fabrication technology, a single PLL is optimal. Distributing the clock with multiple PLLs will not be interesting for the 130-nm technology generation either. At the 100-nm node, the emergence of chips with four PLLs is projected.
AB - This paper discusses clock distribution for chips with multiple microprocessor cores. A model for clock distribution with an array of phase-locked loops (PLLs) is introduced. The model is used to derive an analytical expression describing the optimal design tradeoff between power dissipation and clock inaccuracy. With parameters typical for a 180-nm fabrication technology, a single PLL is optimal. Distributing the clock with multiple PLLs will not be interesting for the 130-nm technology generation either. At the 100-nm node, the emergence of chips with four PLLs is projected.
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U2 - 10.1109/MWSCAS.2001.986210
DO - 10.1109/MWSCAS.2001.986210
M3 - Article
AN - SCOPUS:0035575290
SN - 1548-3746
VL - 1
SP - 454
EP - 457
JO - Midwest Symposium on Circuits and Systems
JF - Midwest Symposium on Circuits and Systems
ER -