Optimal topology exploration for application-specific 3D architectures

Ozcan Ozturk, Feng Wang, Mahmut Kandemir, Yuan Xie

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Scopus citations


As technology scales, increasing interconnect costs make it necessary to consider alternate ways of building integrated circuits. One promising option along this direction is 3D architectures where a stack of multiple device layers, with direct vertical tunneling through them, are put together on the same chip. In this paper, we explore how processor cores and storage blocks can be placed in a 3D architecture to minimize data access costs under temperature constraints. This process is referred to as the topology exploration. Using integer linear programming, we compare the best 2D placement with the best 3D placement, and show through experiments with both single-core and multi-core systems that the 3D placement generates much better results (in terms of data access costs) under the same temperature bounds. We also discuss the tradeoffs between temperature constraint and data access costs.

Original languageEnglish (US)
Title of host publicationProceedings of the ASP-DAC 2006
Subtitle of host publicationAsia and South Pacific Design Automation Conference 2006
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages6
ISBN (Print)0780394518, 9780780394513
StatePublished - 2006
EventASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006 - Yokohama, Japan
Duration: Jan 24 2006Jan 27 2006

Publication series

NameProceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC


OtherASP-DAC 2006: Asia and South Pacific Design Automation Conference 2006

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering


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