Optimization of 3D stack for electrical and thermal integrity

Rishik Bazaz; Jianyong Xie; Madhavan Swaminathan

doi:10.1109/ECTC.2013.6575545

Optimization of 3D stack for electrical and thermal integrity

Rishik Bazaz, Jianyong Xie, Madhavan Swaminathan

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias (TSV) in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity in a co-design. In this paper, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit the thermal and power integrity.

Original language	English (US)
Title of host publication	2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
Pages	22-28
Number of pages	7
DOIs	https://doi.org/10.1109/ECTC.2013.6575545
State	Published - 2013
Event	2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 - Las Vegas, NV, United States Duration: May 28 2013 → May 31 2013

Publication series

Name	Proceedings - Electronic Components and Technology Conference
ISSN (Print)	0569-5503

Conference

Conference	2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013
Country/Territory	United States
City	Las Vegas, NV
Period	5/28/13 → 5/31/13

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Access to Document

10.1109/ECTC.2013.6575545

Cite this

@inproceedings{031a293347024973890fb605e50902a7,

title = "Optimization of 3D stack for electrical and thermal integrity",

abstract = "Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias (TSV) in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity in a co-design. In this paper, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit the thermal and power integrity.",

author = "Rishik Bazaz and Jianyong Xie and Madhavan Swaminathan",

year = "2013",

doi = "10.1109/ECTC.2013.6575545",

language = "English (US)",

isbn = "9781479902330",

series = "Proceedings - Electronic Components and Technology Conference",

pages = "22--28",

booktitle = "2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013",

note = "2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013 ; Conference date: 28-05-2013 Through 31-05-2013",

}

Bazaz, R, Xie, J & Swaminathan, M 2013, Optimization of 3D stack for electrical and thermal integrity. in 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013., 6575545, Proceedings - Electronic Components and Technology Conference, pp. 22-28, 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013, Las Vegas, NV, United States, 5/28/13. https://doi.org/10.1109/ECTC.2013.6575545

TY - GEN

T1 - Optimization of 3D stack for electrical and thermal integrity

AU - Bazaz, Rishik

AU - Xie, Jianyong

AU - Swaminathan, Madhavan

PY - 2013

Y1 - 2013

N2 - Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias (TSV) in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity in a co-design. In this paper, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit the thermal and power integrity.

AB - Heat dissipation causing temperature increase has posed new challenges for design of 3D integrated circuits (IC). In addition to the thermal problem, 3D ICs also require careful design of power grids/network because many inter-tier resistive through-silicon vias (TSV) in 3D IC can cause larger voltage drop than 2D ICs. The performance optimization of a 3D stack requires validation of thermal and electrical integrity in a co-design. In this paper, we perform steady-state electrical and thermal simulations to analyze the properties of a 3D stack. We optimize electrical and thermal performance using genetic algorithm to achieve optimized power map profile for minimizing voltage drop and temperature, which can benefit the thermal and power integrity.

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DO - 10.1109/ECTC.2013.6575545

M3 - Conference contribution

AN - SCOPUS:84883343902

SN - 9781479902330

T3 - Proceedings - Electronic Components and Technology Conference

SP - 22

EP - 28

BT - 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013

T2 - 2013 IEEE 63rd Electronic Components and Technology Conference, ECTC 2013

Y2 - 28 May 2013 through 31 May 2013

ER -

Optimization of 3D stack for electrical and thermal integrity

Abstract

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Conference

All Science Journal Classification (ASJC) codes

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