TY - GEN
T1 - Optimizing bus energy consumption of on-chip multiprocessors using frequent values
AU - Liu, Chun
AU - Sivasubramaniam, Anand
AU - Kandemir, Mahmut
N1 - Funding Information:
Anand Sivasubramaniam received his B.Tech. in Computer Science from the Indian Institute of Technology, Madras, in 1989, and the M.S. and Ph.D. degrees in Computer Science from the Georgia Institute of Technology in 1991 and 1995, respectively. He has been on the faculty at The Pennsylvania State University since Fall 1995 where he is currently a Professor. Anand’s research interests are in computer architecture, operating systems, performance evaluation, and applications for both high performance computer systems and embedded systems. Anand’s research has been funded by NSF through several grants, including the CAREER award, and from industries including IBM, Microsoft and Unisys Corp. He has several publications in leading journals and conferences, and is on the editorial board of IEEE Transactions on Computers and IEEE Transactions on Parallel and Distributed Systems. He is a recipient of the 2002 and 2004 IBM Faculty Awards. Anand is a member of the IEEE, IEEE Computer Society, and ACM.
Funding Information:
This research has been supported in part by NSF grants 0103583, 0130143 and Career Award 0093082.
PY - 2004
Y1 - 2004
N2 - Chip Multiprocessors (CMP) are a convenient way of leveraging from the technological trends to build high-end and embedded systems that are performance and power efficient, while exhibiting attractive properties such as scalability, reliability and ease of design. However, the on-chip interconnect for moving the data between the processors, and between the processors and memory subsystem, plays a crucial role in CMP design. This paper presents a novel approach to optimizing its power by exploiting the value locality in data transfers between processors. A Communicating Value Cache (CVC) is proposed to reduce the number of bits transferred on the interconnect, and simulation results with several parallel applications show significant energy savings with this mechanism. Results show that the importance of our proposal will become even more significant in the future.
AB - Chip Multiprocessors (CMP) are a convenient way of leveraging from the technological trends to build high-end and embedded systems that are performance and power efficient, while exhibiting attractive properties such as scalability, reliability and ease of design. However, the on-chip interconnect for moving the data between the processors, and between the processors and memory subsystem, plays a crucial role in CMP design. This paper presents a novel approach to optimizing its power by exploiting the value locality in data transfers between processors. A Communicating Value Cache (CVC) is proposed to reduce the number of bits transferred on the interconnect, and simulation results with several parallel applications show significant energy savings with this mechanism. Results show that the importance of our proposal will become even more significant in the future.
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U2 - 10.1016/j.matchemphys.2004.01.026
DO - 10.1016/j.matchemphys.2004.01.026
M3 - Conference contribution
AN - SCOPUS:3042572561
SN - 0769520839
SN - 9780769520834
T3 - Proceedings - Euromicro Conference on Parellel, Distribeted and Network-based Proceeding
SP - 340
EP - 347
BT - Proceedings - 12th Euromicro Conference on Parallel, Distributed and Network-based Proceedings, PDP 2004
PB - IEEE Computer Society
T2 - Proceedings - 12th Euromicro Conference on Parallel, Distributed and Network-based Proceedings, PDP 2004
Y2 - 11 February 2004 through 13 February 2004
ER -
