Chip multiprocessors (CMP) are a convenient way of leveraging from the technological trends to build high-end and embedded systems that are performance and power efficient, while exhibiting attractive properties such as scalability, reliability and ease of design. However, the on-chip interconnect for moving the data between the processors, and between the processors and memory subsystem, plays a crucial role in CMP design. This paper presents a novel approach to optimizing its power by exploiting the value locality in data transfers between processors. A communicating value cache (CVC) is proposed to reduce the number of bits transferred on the interconnect, and simulation results with several parallel applications show significant energy savings with this mechanism. Results show that the importance of our proposal will become even more significant in the future.
|Number of pages
|Journal of Systems Architecture
|Published - Feb 2006
|Parallel, Distributed and Network-Based Processing -
Duration: Feb 11 2004 → Feb 13 2004
All Science Journal Classification (ASJC) codes
- Hardware and Architecture