TY - JOUR
T1 - Optimizing bus energy consumption of on-chip multiprocessors using frequent values
AU - Liu, Chun
AU - Sivasubramaniam, Anand
AU - Kandemir, Mahmut
N1 - Funding Information:
Anand Sivasubramaniam received his B.Tech. in Computer Science from the Indian Institute of Technology, Madras, in 1989, and the M.S. and Ph.D. degrees in Computer Science from the Georgia Institute of Technology in 1991 and 1995, respectively. He has been on the faculty at The Pennsylvania State University since Fall 1995 where he is currently a Professor. Anand’s research interests are in computer architecture, operating systems, performance evaluation, and applications for both high performance computer systems and embedded systems. Anand’s research has been funded by NSF through several grants, including the CAREER award, and from industries including IBM, Microsoft and Unisys Corp. He has several publications in leading journals and conferences, and is on the editorial board of IEEE Transactions on Computers and IEEE Transactions on Parallel and Distributed Systems. He is a recipient of the 2002 and 2004 IBM Faculty Awards. Anand is a member of the IEEE, IEEE Computer Society, and ACM.
PY - 2006/2
Y1 - 2006/2
N2 - Chip multiprocessors (CMP) are a convenient way of leveraging from the technological trends to build high-end and embedded systems that are performance and power efficient, while exhibiting attractive properties such as scalability, reliability and ease of design. However, the on-chip interconnect for moving the data between the processors, and between the processors and memory subsystem, plays a crucial role in CMP design. This paper presents a novel approach to optimizing its power by exploiting the value locality in data transfers between processors. A communicating value cache (CVC) is proposed to reduce the number of bits transferred on the interconnect, and simulation results with several parallel applications show significant energy savings with this mechanism. Results show that the importance of our proposal will become even more significant in the future.
AB - Chip multiprocessors (CMP) are a convenient way of leveraging from the technological trends to build high-end and embedded systems that are performance and power efficient, while exhibiting attractive properties such as scalability, reliability and ease of design. However, the on-chip interconnect for moving the data between the processors, and between the processors and memory subsystem, plays a crucial role in CMP design. This paper presents a novel approach to optimizing its power by exploiting the value locality in data transfers between processors. A communicating value cache (CVC) is proposed to reduce the number of bits transferred on the interconnect, and simulation results with several parallel applications show significant energy savings with this mechanism. Results show that the importance of our proposal will become even more significant in the future.
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U2 - 10.1016/j.sysarc.2004.10.009
DO - 10.1016/j.sysarc.2004.10.009
M3 - Conference article
AN - SCOPUS:30744439089
SN - 1383-7621
VL - 52
SP - 129
EP - 142
JO - Journal of Systems Architecture
JF - Journal of Systems Architecture
IS - 2
T2 - Parallel, Distributed and Network-Based Processing
Y2 - 11 February 2004 through 13 February 2004
ER -