Optimizing leakage energy consumption in cache bitlines

Soontae Kim, Narayanan Vijaykrishnan, Mahmut Kandemir, Mary Jane Irwin

Research output: Contribution to journalArticlepeer-review

3 Scopus citations


As technology scales down into deep-submicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit and caches constitute a large portion of the die area. Therefore, there has been much effort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline leakage energy is critical as well. To this end, we propose a predictive precharging scheme to reduce bitline leakage energy consumption. Results show that energy savings are significant with little performance degradation. Also, our predictive precharging is more beneficial in more aggressively scaled technologies.

Original languageEnglish (US)
Pages (from-to)5-18
Number of pages14
JournalDesign Automation for Embedded Systems
Issue number1
StatePublished - Mar 2005

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture


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