TY - GEN
T1 - Package Power Delivery Architecture for High Performance Computing Systems With a 1 kW IVR Operated in CCM-DCM Boundary Mode Condition
AU - Khorasani, Ramin Rahimzadeh
AU - Li, Xingchen
AU - Kim, Joon Woo
AU - Murali, Prahalad
AU - Sharma, Rohit
AU - Swaminathan, Madhavan
N1 - Publisher Copyright:
© 2024 IEEE.
PY - 2024
Y1 - 2024
N2 - This paper investigates a package power delivery architecture for high-performance computing (HPC), incorporating a novel modular multi-phase integrated voltage regulator (IVR). The 1-kW 48-12/1 V architecture integrates an efficient interleaved buck-derived converter at the continuous-discontinuous boundary condition, facilitating parallel-connected networks of embedded inductors to deliver hundreds of amperes per phase. Due to the increased duty cycle and zero switching losses provided for the high side switch, the converter's frequency can be further increased up to 50 MHz with 8 parallel phases and 100 MHz with 16 parallel phases for a 48/1 V, 1 kW architecture. A conceptual 3-D stacked architecture using stacked glass substrates with flip chip GaN switches and embedded inductors, and capacitors is presented, offering a high-density single-stage 48-12/1 V IVR for the next generation of data center applications.
AB - This paper investigates a package power delivery architecture for high-performance computing (HPC), incorporating a novel modular multi-phase integrated voltage regulator (IVR). The 1-kW 48-12/1 V architecture integrates an efficient interleaved buck-derived converter at the continuous-discontinuous boundary condition, facilitating parallel-connected networks of embedded inductors to deliver hundreds of amperes per phase. Due to the increased duty cycle and zero switching losses provided for the high side switch, the converter's frequency can be further increased up to 50 MHz with 8 parallel phases and 100 MHz with 16 parallel phases for a 48/1 V, 1 kW architecture. A conceptual 3-D stacked architecture using stacked glass substrates with flip chip GaN switches and embedded inductors, and capacitors is presented, offering a high-density single-stage 48-12/1 V IVR for the next generation of data center applications.
UR - https://www.scopus.com/pages/publications/85197705507
UR - https://www.scopus.com/pages/publications/85197705507#tab=citedBy
U2 - 10.1109/ECTC51529.2024.00054
DO - 10.1109/ECTC51529.2024.00054
M3 - Conference contribution
AN - SCOPUS:85197705507
T3 - Proceedings - Electronic Components and Technology Conference
SP - 285
EP - 292
BT - Proceedings - IEEE 74th Electronic Components and Technology Conference, ECTC 2024
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 74th IEEE Electronic Components and Technology Conference, ECTC 2024
Y2 - 28 May 2024 through 31 May 2024
ER -