Packaging of multi-core microprocessors: Tradeoffs and potential solutions

Prathap Muthana; Madhavan Swaminathan; Rao Tummala; Venkatesh Sundaram; Lixi Wan; S. K. Bhattacharya; P. M. Raj

Packaging of multi-core microprocessors: Tradeoffs and potential solutions

Prathap Muthana
, Madhavan Swaminathan
, Rao Tummala
, Venkatesh Sundaram
, Lixi Wan
, S. K. Bhattacharya
, P. M. Raj

Electrical Engineering

Research output: Contribution to journal › Conference article › peer-review

7 Scopus citations

Abstract

Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multi-core processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade off's between single and multi-core processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.

Original language	English (US)
Pages (from-to)	1895-1903
Number of pages	9
Journal	Proceedings - Electronic Components and Technology Conference
Volume	2
State	Published - 2005
Event	55th Electronic Components and Technology Conference, ECTC - Lake Buena Vista, FL, United States Duration: May 31 2005 → Jun 4 2005

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Electrical and Electronic Engineering

Cite this

@article{2c84f01ca0834333b54004f9ea632e82,

title = "Packaging of multi-core microprocessors: Tradeoffs and potential solutions",

abstract = "Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multi-core processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade off's between single and multi-core processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.",

author = "Prathap Muthana and Madhavan Swaminathan and Rao Tummala and Venkatesh Sundaram and Lixi Wan and Bhattacharya, \{S. K.\} and Raj, \{P. M.\}",

year = "2005",

language = "English (US)",

volume = "2",

pages = "1895--1903",

journal = "Proceedings - Electronic Components and Technology Conference",

issn = "0569-5503",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "55th Electronic Components and Technology Conference, ECTC ; Conference date: 31-05-2005 Through 04-06-2005",

}

TY - JOUR

T1 - Packaging of multi-core microprocessors

T2 - 55th Electronic Components and Technology Conference, ECTC

AU - Muthana, Prathap

AU - Swaminathan, Madhavan

AU - Tummala, Rao

AU - Sundaram, Venkatesh

AU - Wan, Lixi

AU - Bhattacharya, S. K.

AU - Raj, P. M.

PY - 2005

Y1 - 2005

N2 - Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multi-core processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade off's between single and multi-core processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.

AB - Power consumption and interconnect latency are becoming major bottlenecks in the design of high performance computers and microprocessors. In this paper we propose to use a multi-core processor approach to improve the performance of a processor. This paper discusses an analysis of the performance trade off's between single and multi-core processors based on power, frequency, bandwidth and the role of embedded passives with high density wiring in future packages to support such processors.

UR - https://www.scopus.com/pages/publications/24644482060

UR - https://www.scopus.com/pages/publications/24644482060#tab=citedBy

M3 - Conference article

AN - SCOPUS:24644482060

SN - 0569-5503

VL - 2

SP - 1895

EP - 1903

JO - Proceedings - Electronic Components and Technology Conference

JF - Proceedings - Electronic Components and Technology Conference

Y2 - 31 May 2005 through 4 June 2005

ER -

Packaging of multi-core microprocessors: Tradeoffs and potential solutions

Abstract

All Science Journal Classification (ASJC) codes

Other files and links

Fingerprint

Cite this