TY - GEN
T1 - Parallel and pipelined VLSI implementation of the new radix-2 DIT FFT algorithm
AU - Samudrala, Harsha Keerthan
AU - Qadeer, Shaik
AU - Azeemuddin, Syed
AU - Khan, Zafar
N1 - Publisher Copyright:
© 2018 IEEE.
PY - 2018/7/2
Y1 - 2018/7/2
N2 - In this paper we discuss the VLSI implementation of the new radix-2 Decimation In Time (DIT) Fast Fourier Transform (FFT) algorithm with reduced arithmetic complexity which is based on scaling the twiddle factor. Some signal processing require high performance FFT processors and to meet these performance requirements, the processor needs to be pipelined and parallelized. An optimized ASIC design is derived from this new radix-2 algorithm with fewer multipliers and adopted a complete parallel and pipelined architecture for hardware implementation of a 64 point FFT. The implementation results show that the proposed architecture significantly reduces the hardware area by 13.74 percent and power consumption by 16 percent when compared to the standard FFT architecture. Simulation of design units is done in Xilinx ISE WebPack 13.1 and synthesized using Cadence Encounter RTL Compiler.
AB - In this paper we discuss the VLSI implementation of the new radix-2 Decimation In Time (DIT) Fast Fourier Transform (FFT) algorithm with reduced arithmetic complexity which is based on scaling the twiddle factor. Some signal processing require high performance FFT processors and to meet these performance requirements, the processor needs to be pipelined and parallelized. An optimized ASIC design is derived from this new radix-2 algorithm with fewer multipliers and adopted a complete parallel and pipelined architecture for hardware implementation of a 64 point FFT. The implementation results show that the proposed architecture significantly reduces the hardware area by 13.74 percent and power consumption by 16 percent when compared to the standard FFT architecture. Simulation of design units is done in Xilinx ISE WebPack 13.1 and synthesized using Cadence Encounter RTL Compiler.
UR - http://www.scopus.com/inward/record.url?scp=85067100609&partnerID=8YFLogxK
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U2 - 10.1109/iSES.2018.00015
DO - 10.1109/iSES.2018.00015
M3 - Conference contribution
AN - SCOPUS:85067100609
T3 - Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018
SP - 21
EP - 26
BT - Proceedings - 2018 IEEE 4th International Symposium on Smart Electronic Systems, iSES 2018
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th IEEE International Symposium on Smart Electronic Systems, iSES 2018
Y2 - 17 December 2018 through 19 December 2018
ER -