PARAMETRIC THERMAL DESIGN FOR HETEROGENEOUSLY INTEGRATED HIGH-POWER PACKAGES

As power densities increase in heterogeneously integrated systems, with the introduction of new 3D architectures and the increasing number of transistors on chips, there exists a continued bottleneck for thermal management. High temperatures have a drastic impact on memory performances and refresh cycles. Moreover, thermal coupling between neighboring chiplets on a package is increasing as the types of chips on a heterogeneously integrated package diversify, and this, in turn, creates different heat flux densities within a heterogeneously integrated package. Thus, there arises a need for the implementation of efficient thermal design and solutions that cater to high heat fluxes within a package as well as different heights for different chip stacks within a package. In this paper, we present a parametric thermal design of heterogeneously integrated packages for high-performance computing. We focus on a 2.5D packaging structure, which includes components including artificial intelligence (AI) accelerators and high bandwidth memory (HBM) on a silicon interposer. Analytically and numerically, we investigate the thermal challenges stemming from high power density in stacked dies, variations in die heights, and cooling limitations at the package surface. To mitigate temperature gradients within the package, we propose a thermal-aware package structure, emphasizing the inside architecture. Also, the thermal coupling effect is studied for multiple cooling technologies on the outer surface using a thermal violation region graph. This research has shown that not only the internal structure of the package but also its ability to transfer heat to the outer surface has a significant impact on the thermal coupling effect. Using our approach, we can design package architecture systematically considering the external cooling environment in the early design stage.