Parasitic extraction and simulation of simultaneous switching noise in on-chip power distribution networks

In this paper, new modeling and simulation techniques for analysis of on-chip power distribution networks are presented. New closed-form expressions for parasitics of the power and ground lines are proposed which consider the effect of lossy silicon substrate, the effect the current return paths through metal layers, and the effect of irregular arrangement of lines. The extraction results are compared against the results from a full-wave solver. Then the effect of current return paths through the metal layers and the effect of irregular arrangement of lines on the parasitics are studied. A transmission line equivalent circuit of the lines is constructed from the parasitics extracted. To capture the variation of parasitics of the line with frequency, the equivalent circuit of the line is augmented with a debye model. Simulation is performed by explicitly solving the kirchoff’s current and voltage laws using a circuit-based finite difference time domain scheme. This scheme is augmented with a frequency dependent formulation to accomadate frequency-dependent parasitics. Using this simulator, the effect of irregular arrangement of lines on the simultaneous switching noise is studied.