@inproceedings{280e49a7052b476489adca33598d6d19,
title = "Partial-product generation and addition for multiplication in FPGAS with 6-input LUTs",
abstract = "Multiplication is the dominant operation for many applications implemented on field-programmable gate arrays (FPGAs). Although most current FPGA families have embedded hard multipliers, soft multipliers using lookup tables (LUTs) in the logic fabric remain important. This paper presents a novel circuit that combines radix-4 partial-product generation with addition (patent pending) and shows how it can be used to implement two's-complement multipliers. Single-cycle and pipelined designs for 8×8, 10×10, 12×12, 14×14 and 16×16 multipliers are compared to Xilinx LogiCORE IP multipliers. Proposed single-cycle parallel-tree multipliers use 35\% to 45\% fewer LUTs and have 9\% to 22\% less delay than LogiCORE IP multipliers. Proposed pipelined parallel-tree multipliers use 32\% to 40\% fewer LUTs than LogiCORE IP multipliers. Proposed parallel-array multipliers use even fewer LUTs than parallel-tree multipliers at the expense of increased delay.",
author = "Walters, \{E. George\}",
year = "2015",
month = apr,
day = "24",
doi = "10.1109/ACSSC.2014.7094659",
language = "English (US)",
series = "Conference Record - Asilomar Conference on Signals, Systems and Computers",
publisher = "IEEE Computer Society",
pages = "1247--1251",
editor = "Matthews, \{Michael B.\}",
booktitle = "Conference Record of the 48th Asilomar Conference on Signals, Systems and Computers",
address = "United States",
note = "48th Asilomar Conference on Signals, Systems and Computers, ACSSC 2015 ; Conference date: 02-11-2014 Through 05-11-2014",
}