@inproceedings{3efc65ed0a514d5c87fb230d946d9aab,
title = "Path planning on the TrueNorth neurosynaptic system",
abstract = "We report on the implementation of a path planning algorithm on the TrueNorth neurosynaptic system. Our implementation exploits processing in the temporal domain within the architectural constraints of the TrueNorth chip to deduce the optimal path. The optimal path is computed on the TrueNorth chip for grid maps with dimensions as large as 173 χ 168 nodes consuming 70.0mW at an operating voltage of 0.8V.",
author = "Fischl, {Kate D.} and Kaitlin Fair and Tsai, {Wei Yu} and Jack Sampson and Andreas Andreou",
note = "Funding Information: ACKNOWLEDGMENT We thank Jeff Krichmar for his insight and Andrew Cassidy and the entire IBM TrueNorth team for their support throughout this work. This paper was partially supported by the National Science Foundation Graduate Research Fellowship under Grant No. DGE-1232825, NSF grant INSPIRE SMA 1248056, NSF Grant 1540916: SL-CN Cortical Architectures for Robust Adaptive Perception and Action through the Telluride Workshop on Neuromorphic Cognition Engineering, and by an ONR MURI N000141010278. This work is also supported in part by NSF Expeditions: Visual Cortex on Silicon CCF 1317560. Publisher Copyright: {\textcopyright} 2017 IEEE.; 50th IEEE International Symposium on Circuits and Systems, ISCAS 2017 ; Conference date: 28-05-2017 Through 31-05-2017",
year = "2017",
month = sep,
day = "25",
doi = "10.1109/ISCAS.2017.8050932",
language = "English (US)",
series = "Proceedings - IEEE International Symposium on Circuits and Systems",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "IEEE International Symposium on Circuits and Systems",
address = "United States",
}