TY - JOUR
T1 - Paving the Way for Pass Disturb-Free Vertical NAND Storage via a Dedicated and String-Compatible Pass Gate
AU - Zhao, Zijian
AU - Woo, Sola
AU - Aabrar, Khandker Akif
AU - Kirtania, Sharadindu Gopal
AU - Jiang, Zhouhang
AU - Deng, Shan
AU - Xiao, Yi
AU - Mulaosmanovic, Halid
AU - Duenkel, Stefan
AU - Kleimaier, Dominik
AU - Soss, Steven
AU - Beyer, Sven
AU - Joshi, Rajiv
AU - Meninger, Scott
AU - Mohamed, Mohamed
AU - Kim, Kijoon
AU - Woo, Jongho
AU - Lim, Suhwan
AU - Kim, Kwangsoo
AU - Kim, Wanki
AU - Ha, Daewon
AU - Narayanan, Vijaykrishnan
AU - Datta, Suman
AU - Yu, Shimeng
AU - Ni, Kai
N1 - Publisher Copyright:
© 2024 American Chemical Society.
PY - 2024
Y1 - 2024
N2 - In this work, we propose a dual-port cell design to address the pass disturbance in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that (i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-VTH (HVT) state and the screening of the applied field by the channel at the low-VTH (LVT) state; (ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; (iii) the proposed design can be incorporated into a highly scaled vertical NAND FeFET string, and the pass gate can be incorporated into the existing three-dimensional (3D) NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate.
AB - In this work, we propose a dual-port cell design to address the pass disturbance in vertical NAND storage, which can pass signals through a dedicated and string-compatible pass gate. We demonstrate that (i) the pass disturb-free feature originates from weakening of the depolarization field by the pass bias at the high-VTH (HVT) state and the screening of the applied field by the channel at the low-VTH (LVT) state; (ii) combined simulations and experimental demonstrations of dual-port design verify the disturb-free operation in a NAND string, overcoming a key challenge in single-port designs; (iii) the proposed design can be incorporated into a highly scaled vertical NAND FeFET string, and the pass gate can be incorporated into the existing three-dimensional (3D) NAND with the negligible overhead of the pass gate interconnection through a global bottom pass gate contact in the substrate.
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U2 - 10.1021/acsami.4c08190
DO - 10.1021/acsami.4c08190
M3 - Article
C2 - 39374172
AN - SCOPUS:85205842769
SN - 1944-8244
JO - ACS Applied Materials and Interfaces
JF - ACS Applied Materials and Interfaces
ER -