TY - GEN
T1 - Performance, energy, and reliability tradeoffs in replicating hot cache lines
AU - Zhang, W.
AU - Kandemir, M.
AU - Sivasubramaniam, A.
AU - Irwin, M. J.
PY - 2003/1/1
Y1 - 2003/1/1
N2 - The importance of L1 data caches makes their performance, power consumption, and data integrity characteristics extremely critical in embedded systems design. We examine these issues in the context of a mechanism that tries to enhance data cache reliability by replicating cache lines (blocks) in active use. When replicating data cache lines, it is important to not evict other lines that may be needed or to not incur very high power consumption. We evaluate the tradeoffs between these three goals (reliability, energy, and performance) by modulating two important parameters, namely, the hot-block threshold and the dead-block threshold. We show that having a hot-block threshold in the range of 10-1000 cycles can provide good reliability characteristics, without compromising on performance or power. At the same time, our results indicate that one could use aggressive dead-block thresholds to provide leakage power savings without compromising on the performance and reliability characteristics. The results from this paper can be used to design power, performance, and reliability enhanced cache architectures.
AB - The importance of L1 data caches makes their performance, power consumption, and data integrity characteristics extremely critical in embedded systems design. We examine these issues in the context of a mechanism that tries to enhance data cache reliability by replicating cache lines (blocks) in active use. When replicating data cache lines, it is important to not evict other lines that may be needed or to not incur very high power consumption. We evaluate the tradeoffs between these three goals (reliability, energy, and performance) by modulating two important parameters, namely, the hot-block threshold and the dead-block threshold. We show that having a hot-block threshold in the range of 10-1000 cycles can provide good reliability characteristics, without compromising on performance or power. At the same time, our results indicate that one could use aggressive dead-block thresholds to provide leakage power savings without compromising on the performance and reliability characteristics. The results from this paper can be used to design power, performance, and reliability enhanced cache architectures.
UR - http://www.scopus.com/inward/record.url?scp=18844451753&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=18844451753&partnerID=8YFLogxK
U2 - 10.1145/951746.951750
DO - 10.1145/951746.951750
M3 - Conference contribution
AN - SCOPUS:18844451753
SN - 1581136765
SN - 9781581136760
T3 - CASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
SP - 309
EP - 317
BT - CASES 2003
PB - Association for Computing Machinery (ACM)
T2 - CASES 2003: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems
Y2 - 30 October 2003 through 1 November 2003
ER -