Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques

Jae Won Jang; Swaroop Ghosh

doi:10.1145/2934583.2934614

Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques

Jae Won Jang, Swaroop Ghosh

Electrical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

7 Scopus citations

Abstract

In this paper, we analyze the fundamental vulnerabilities of Spin-Torque-Transfer RAM on magnetic field and temperature that can be exploited by adversaries with an intent to trigger soft performance failures. We present novel attack vectors and their impact on memory performance (i.e., read, write and retention). We propose a novel low-overhead clock frequency-adaptation technique to mitigate the attack. Our analysis indicate slowing the clock frequency by 85% restores 170 mV of sense margin under 300 Oe DC magnetic field. In addition, 66% operating clock slowdown allows STTRAM to tolerate over 300 Oe AC magnetic field.

Original language	English (US)
Title of host publication	ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	136-141
Number of pages	6
ISBN (Electronic)	9781450341851
DOIs	https://doi.org/10.1145/2934583.2934614
State	Published - Aug 8 2016
Event	21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016 - San Francisco, United States Duration: Aug 8 2016 → Aug 10 2016

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016
Country/Territory	United States
City	San Francisco
Period	8/8/16 → 8/10/16

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1145/2934583.2934614

Cite this

Jang, J. W., & Ghosh, S. (2016). Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques. In ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design (pp. 136-141). (Proceedings of the International Symposium on Low Power Electronics and Design). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2934583.2934614

Jang, Jae Won ; Ghosh, Swaroop. / Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques. ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2016. pp. 136-141 (Proceedings of the International Symposium on Low Power Electronics and Design).

@inproceedings{3c6d1fd87fc744a297c663559c8adc1a,

title = "Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques",

abstract = "In this paper, we analyze the fundamental vulnerabilities of Spin-Torque-Transfer RAM on magnetic field and temperature that can be exploited by adversaries with an intent to trigger soft performance failures. We present novel attack vectors and their impact on memory performance (i.e., read, write and retention). We propose a novel low-overhead clock frequency-adaptation technique to mitigate the attack. Our analysis indicate slowing the clock frequency by 85% restores 170 mV of sense margin under 300 Oe DC magnetic field. In addition, 66% operating clock slowdown allows STTRAM to tolerate over 300 Oe AC magnetic field.",

author = "Jang, {Jae Won} and Swaroop Ghosh",

note = "Publisher Copyright: {\textcopyright} 2016 ACM.; 21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016 ; Conference date: 08-08-2016 Through 10-08-2016",

year = "2016",

month = aug,

day = "8",

doi = "10.1145/2934583.2934614",

language = "English (US)",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "136--141",

booktitle = "ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design",

address = "United States",

}

Jang, JW & Ghosh, S 2016, Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques. in ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, Institute of Electrical and Electronics Engineers Inc., pp. 136-141, 21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016, San Francisco, United States, 8/8/16. https://doi.org/10.1145/2934583.2934614

Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques. / Jang, Jae Won; Ghosh, Swaroop.
ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc., 2016. p. 136-141 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques

AU - Jang, Jae Won

AU - Ghosh, Swaroop

PY - 2016/8/8

Y1 - 2016/8/8

N2 - In this paper, we analyze the fundamental vulnerabilities of Spin-Torque-Transfer RAM on magnetic field and temperature that can be exploited by adversaries with an intent to trigger soft performance failures. We present novel attack vectors and their impact on memory performance (i.e., read, write and retention). We propose a novel low-overhead clock frequency-adaptation technique to mitigate the attack. Our analysis indicate slowing the clock frequency by 85% restores 170 mV of sense margin under 300 Oe DC magnetic field. In addition, 66% operating clock slowdown allows STTRAM to tolerate over 300 Oe AC magnetic field.

AB - In this paper, we analyze the fundamental vulnerabilities of Spin-Torque-Transfer RAM on magnetic field and temperature that can be exploited by adversaries with an intent to trigger soft performance failures. We present novel attack vectors and their impact on memory performance (i.e., read, write and retention). We propose a novel low-overhead clock frequency-adaptation technique to mitigate the attack. Our analysis indicate slowing the clock frequency by 85% restores 170 mV of sense margin under 300 Oe DC magnetic field. In addition, 66% operating clock slowdown allows STTRAM to tolerate over 300 Oe AC magnetic field.

UR - http://www.scopus.com/inward/record.url?scp=85041659030&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85041659030&partnerID=8YFLogxK

U2 - 10.1145/2934583.2934614

DO - 10.1145/2934583.2934614

M3 - Conference contribution

AN - SCOPUS:85041659030

T3 - Proceedings of the International Symposium on Low Power Electronics and Design

SP - 136

EP - 141

BT - ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 21st IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2016

Y2 - 8 August 2016 through 10 August 2016

ER -

Jang JW, Ghosh S. Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques. In ISLPED 2016 - Proceedings of the 2016 International Symposium on Low Power Electronics and Design. Institute of Electrical and Electronics Engineers Inc. 2016. p. 136-141. (Proceedings of the International Symposium on Low Power Electronics and Design). doi: 10.1145/2934583.2934614

Performance Impact of Magnetic and Thermal Attack on STTRAM and Low-Overhead Mitigation Techniques

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