Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs

Priya Sundararajan; Sridhar Krishnamurthy; N. Vijaykrishnan; Kamal Chaudhary; Rajeev Jayaraman

doi:10.1109/SOCC.2006.283857

Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs

Priya Sundararajan, Sridhar Krishnamurthy, N. Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) Optimal register placement algorithms within the DSP48 block and (ii) Timing driven mechanism to have maximal pipeline depth.

Original language	English (US)
Title of host publication	2006 IEEE International Systems-on-Chip Conference, SOC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	105-106
Number of pages	2
ISBN (Print)	0780397819, 9780780397811
DOIs	https://doi.org/10.1109/SOCC.2006.283857
State	Published - Jan 1 2006
Event	2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States Duration: Sep 24 2006 → Sep 27 2006

Publication series

Name	2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other	2006 IEEE International Systems-on-Chip Conference, SOC
Country/Territory	United States
City	Austin, TX
Period	9/24/06 → 9/27/06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/SOCC.2006.283857

Cite this

Sundararajan, P., Krishnamurthy, S., Vijaykrishnan, N., Chaudhary, K., & Jayaraman, R. (2006). Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs. In 2006 IEEE International Systems-on-Chip Conference, SOC (pp. 105-106). Article 4063026 (2006 IEEE International Systems-on-Chip Conference, SOC). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/SOCC.2006.283857

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title = "Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs",

abstract = "Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) Optimal register placement algorithms within the DSP48 block and (ii) Timing driven mechanism to have maximal pipeline depth.",

author = "Priya Sundararajan and Sridhar Krishnamurthy and N. Vijaykrishnan and Kamal Chaudhary and Rajeev Jayaraman",

year = "2006",

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doi = "10.1109/SOCC.2006.283857",

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isbn = "0780397819",

series = "2006 IEEE International Systems-on-Chip Conference, SOC",

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Sundararajan, P, Krishnamurthy, S, Vijaykrishnan, N, Chaudhary, K & Jayaraman, R 2006, Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs. in 2006 IEEE International Systems-on-Chip Conference, SOC., 4063026, 2006 IEEE International Systems-on-Chip Conference, SOC, Institute of Electrical and Electronics Engineers Inc., pp. 105-106, 2006 IEEE International Systems-on-Chip Conference, SOC, Austin, TX, United States, 9/24/06. https://doi.org/10.1109/SOCC.2006.283857

Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs. / Sundararajan, Priya; Krishnamurthy, Sridhar; Vijaykrishnan, N. et al.
2006 IEEE International Systems-on-Chip Conference, SOC. Institute of Electrical and Electronics Engineers Inc., 2006. p. 105-106 4063026 (2006 IEEE International Systems-on-Chip Conference, SOC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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AU - Jayaraman, Rajeev

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AB - Platform FPGAs have introduced complex reconfigurable black-boxes for complete system on chip implementation. With rising expectations from these architectures there is a need to perform optimizations across the FPGA slice fabric and the newly introduced black boxes to maximize performance gains. In this paper, we discuss a timing driven reconfiguration technique to improve performance of DSP designs on platform FPGAs by (i) Optimal register placement algorithms within the DSP48 block and (ii) Timing driven mechanism to have maximal pipeline depth.

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T3 - 2006 IEEE International Systems-on-Chip Conference, SOC

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BT - 2006 IEEE International Systems-on-Chip Conference, SOC

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Sundararajan P, Krishnamurthy S, Vijaykrishnan N, Chaudhary K, Jayaraman R. Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs. In 2006 IEEE International Systems-on-Chip Conference, SOC. Institute of Electrical and Electronics Engineers Inc. 2006. p. 105-106. 4063026. (2006 IEEE International Systems-on-Chip Conference, SOC). doi: 10.1109/SOCC.2006.283857

Performance improvements through timing driven reconfiguration of black-boxes in platform FPGAs

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