Phase-aware adaptive hardware selection for power-efficient scientific computations

Konrad Malkowski; Padma Raghavan; Mahmut Kandemir; Mary Jane Irwin

doi:10.1145/1283780.1283869

Phase-aware adaptive hardware selection for power-efficient scientific computations

Konrad Malkowski, Padma Raghavan, Mahmut Kandemir, Mary Jane Irwin

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

Increased power consumption and heat dissipation have become the major limiters of available computational resources at many high performance computing (HPC) centers. Applications that run at suchcenters typically operate in single user mode, run for longperiods of time, and have long lasting application phases. Their users are interested in obtaining the maximum performance. We propose a phase aware adaptive hardware selection technique,featuring data prefetchers and dynamic voltage and frequency scaling. Ourtechnique takes advantage of memory bound phases in scientific codes, resulting in significant power (39%) and energy (37%) reductions while maintainingor exceeding the performance of an unoptimized system.

Original language	English (US)
Title of host publication	ISLPED'07
Subtitle of host publication	Proceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages	403-406
Number of pages	4
DOIs	https://doi.org/10.1145/1283780.1283869
State	Published - 2007
Event	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States Duration: Aug 27 2007 → Aug 29 2007

Publication series

Name	Proceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)	1533-4678

Other

Other	ISLPED'07: 2007 International Symposium on Low Power Electronics and Design
Country/Territory	United States
City	Portland, OR
Period	8/27/07 → 8/29/07

All Science Journal Classification (ASJC) codes

General Engineering

Access to Document

10.1145/1283780.1283869

Cite this

Malkowski, K., Raghavan, P., Kandemir, M., & Irwin, M. J. (2007). Phase-aware adaptive hardware selection for power-efficient scientific computations. In ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 403-406). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283869

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title = "Phase-aware adaptive hardware selection for power-efficient scientific computations",

abstract = "Increased power consumption and heat dissipation have become the major limiters of available computational resources at many high performance computing (HPC) centers. Applications that run at suchcenters typically operate in single user mode, run for longperiods of time, and have long lasting application phases. Their users are interested in obtaining the maximum performance. We propose a phase aware adaptive hardware selection technique,featuring data prefetchers and dynamic voltage and frequency scaling. Ourtechnique takes advantage of memory bound phases in scientific codes, resulting in significant power (39%) and energy (37%) reductions while maintainingor exceeding the performance of an unoptimized system.",

author = "Konrad Malkowski and Padma Raghavan and Mahmut Kandemir and Irwin, {Mary Jane}",

year = "2007",

doi = "10.1145/1283780.1283869",

language = "English (US)",

isbn = "1595937099",

series = "Proceedings of the International Symposium on Low Power Electronics and Design",

pages = "403--406",

booktitle = "ISLPED'07",

note = "ISLPED'07: 2007 International Symposium on Low Power Electronics and Design ; Conference date: 27-08-2007 Through 29-08-2007",

}

Malkowski, K, Raghavan, P, Kandemir, M & Irwin, MJ 2007, Phase-aware adaptive hardware selection for power-efficient scientific computations. in ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. Proceedings of the International Symposium on Low Power Electronics and Design, pp. 403-406, ISLPED'07: 2007 International Symposium on Low Power Electronics and Design, Portland, OR, United States, 8/27/07. https://doi.org/10.1145/1283780.1283869

Phase-aware adaptive hardware selection for power-efficient scientific computations. / Malkowski, Konrad; Raghavan, Padma; Kandemir, Mahmut et al.
ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design. 2007. p. 403-406 (Proceedings of the International Symposium on Low Power Electronics and Design).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Phase-aware adaptive hardware selection for power-efficient scientific computations

AU - Malkowski, Konrad

AU - Raghavan, Padma

AU - Kandemir, Mahmut

AU - Irwin, Mary Jane

PY - 2007

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N2 - Increased power consumption and heat dissipation have become the major limiters of available computational resources at many high performance computing (HPC) centers. Applications that run at suchcenters typically operate in single user mode, run for longperiods of time, and have long lasting application phases. Their users are interested in obtaining the maximum performance. We propose a phase aware adaptive hardware selection technique,featuring data prefetchers and dynamic voltage and frequency scaling. Ourtechnique takes advantage of memory bound phases in scientific codes, resulting in significant power (39%) and energy (37%) reductions while maintainingor exceeding the performance of an unoptimized system.

AB - Increased power consumption and heat dissipation have become the major limiters of available computational resources at many high performance computing (HPC) centers. Applications that run at suchcenters typically operate in single user mode, run for longperiods of time, and have long lasting application phases. Their users are interested in obtaining the maximum performance. We propose a phase aware adaptive hardware selection technique,featuring data prefetchers and dynamic voltage and frequency scaling. Ourtechnique takes advantage of memory bound phases in scientific codes, resulting in significant power (39%) and energy (37%) reductions while maintainingor exceeding the performance of an unoptimized system.

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T3 - Proceedings of the International Symposium on Low Power Electronics and Design

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BT - ISLPED'07

T2 - ISLPED'07: 2007 International Symposium on Low Power Electronics and Design

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ER -

Phase-aware adaptive hardware selection for power-efficient scientific computations

Abstract

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Other

All Science Journal Classification (ASJC) codes

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