TY - GEN
T1 - Physically Addressed Queueing (PAQ)
T2 - 2012 39th Annual International Symposium on Computer Architecture, ISCA 2012
AU - Jung, Myoungsoo
AU - Wilson, Ellis H.
AU - Kandemir, Mahmut
PY - 2012
Y1 - 2012
N2 - NAND flash storage has proven to be a competitive alternative to traditional disk for its properties of high random-access speeds, low-power and its presumed efficacy for random-reads. Ironically, we demonstrate that when packaged in SSD format, there arise many barriers to reaching full parallelism in reads, resulting in random writes outperforming them. Motivated by this, we propose Physically Addressed Queuing (PAQ), a request scheduler that avoids resource contention resultant from shared SSD resources. PAQ makes the following major contributions: First, it exposes the physical addresses of requests to the scheduler. Second, I/O clumping is utilized to select groups of operations that can be simultaneously executed without major resource conflict. Third, inter-request NAND transaction packing empowers multi-plane-mode operations. We implement PAQ in a cycle-accurate simulator and demonstrate bandwidth and IOPS improvements greater than 62% and latency decreases as much as 41.6% for random reads, without degrading performance of other access types.
AB - NAND flash storage has proven to be a competitive alternative to traditional disk for its properties of high random-access speeds, low-power and its presumed efficacy for random-reads. Ironically, we demonstrate that when packaged in SSD format, there arise many barriers to reaching full parallelism in reads, resulting in random writes outperforming them. Motivated by this, we propose Physically Addressed Queuing (PAQ), a request scheduler that avoids resource contention resultant from shared SSD resources. PAQ makes the following major contributions: First, it exposes the physical addresses of requests to the scheduler. Second, I/O clumping is utilized to select groups of operations that can be simultaneously executed without major resource conflict. Third, inter-request NAND transaction packing empowers multi-plane-mode operations. We implement PAQ in a cycle-accurate simulator and demonstrate bandwidth and IOPS improvements greater than 62% and latency decreases as much as 41.6% for random reads, without degrading performance of other access types.
UR - http://www.scopus.com/inward/record.url?scp=84864842466&partnerID=8YFLogxK
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U2 - 10.1109/ISCA.2012.6237035
DO - 10.1109/ISCA.2012.6237035
M3 - Conference contribution
AN - SCOPUS:84864842466
SN - 9781467304757
T3 - Proceedings - International Symposium on Computer Architecture
SP - 404
EP - 415
BT - 2012 39th Annual International Symposium on Computer Architecture, ISCA 2012
Y2 - 9 June 2012 through 13 June 2012
ER -