@inproceedings{e0dbd7d5ed724a7b97142c95fa2bab05,
title = "POSTER: Location-Aware Computation Mapping for Manycore Processors",
abstract = "Employing an on-chip network in a manycore system (to improve scalability) makes the latencies of data accesses issued by a core non-uniform, which significant impact application performance. This paper presents a compiler strategy which involves exposing architecture information to the compiler to enable optimized computation-to-core mapping. Our scheme takes into account the relative positions of (and distances between) cores, last-level caches (LLCs) and memory controllers (MCs) in a manycore system, and generates a mapping of computations to cores with the goal of minimizing the on-chip network traffic. Our experiments of 12 multi-threaded applications reveal that, on average, our approach reduces the on-chip network latency in a 6x6 manycore system by 49.5\% in the case of private LLCs and 52.7\% in the case of shared LLCs. These improvements translate to the corresponding execution time improvements of 14.8\% and 15.2\% for the private LLC and shared LLC based systems.",
author = "Orhan Kislal and Jagadish Kotra and Xulong Tang and Kandemir, \{Mahmut Taylan\} and Myoungsoo Jung",
year = "2017",
month = oct,
day = "31",
doi = "10.1109/PACT.2017.20",
language = "English (US)",
series = "Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "138--139",
booktitle = "Proceedings - 26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017",
address = "United States",
note = "26th International Conference on Parallel Architectures and Compilation Techniques, PACT 2017 ; Conference date: 09-09-2017 Through 13-09-2017",
}