Power analysis of interconnect structures

Yan Zhang, Wu Ye, Robert M. Owens, Mary Jane Irwin

Research output: Contribution to journalConference articlepeer-review

2 Scopus citations


Interconnect structures play a more and more important role in low power computer design. Yet few investigations have been done in power analysis of interconnect structures. In this paper five designs of interconnect structures are implemented and a power analysis of interconnect structures that vary at the architecture level and gate level for different numbers of input ports is presented. The results based on these designs show that MUXes implemented with n-type pass transistors consume the least total power and set up power (power consumption in setting up the transmitting path). Crossbars consume the least transfer power (power consumption in transferring data). Muxes implemented with SPSD (Sympathetic Precharge Static Domino) gates have relatively lower delay especially for high fan-in interconnect structures. MUXes implemented with pass transistors have the lowest power-delay product for input ports numbers of 4, 8 and 16 while MUXes implemented with SPSD gates have the lowest power-delay product for interconnect structures which have 32 input ports.

Original languageEnglish (US)
Pages (from-to)25-29
Number of pages5
JournalProceedings of the Annual IEEE International ASIC Conference and Exhibit
StatePublished - Jan 1 1997
EventProceedings of the 1997 10th Annual IEEE International ASIC Conference and Exhibit - Portland, OR, USA
Duration: Sep 7 1997Sep 10 1997

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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