Traditionally, buses have been traditionally used as datapath interconnects because of their simplicity. Yet, as technology quickly scales down and the industry embraces systems-on-A-chip (SoC), the increasing global interconnect delay and chip power consumption become big concerns, and alternative datapath interconnect structures should be considered. This paper evaluates two datapath interconnection alternatives-full connection crossbars and multiple-input/output-port buses-At the transistor level and compares their power and delay performances. The results show that although a full connection crossbar consumes more energy per cycle and incurs larger delays than buses, crossbars consume less energy per data transfer when the number of input/output ports is small and the crossbar operates in full parallelism. This makes crossbars a good choice for connecting components and transferring parallel data in SoC designs.