Power-efficient trace caches

J. S. Hu; N. Vijaykrishnan; A. Kandemir; A. J. Irwin

doi:10.1109/DATE.2002.999209

Power-efficient trace caches

J. S. Hu, N. Vijaykrishnan, A. Kandemir, A. J. Irwin

Research output: Contribution to journal › Conference article › peer-review

6 Scopus citations

Abstract

This paper exploits the drawbacks of wasting power when accessing the instruction cache that stores only static sequence of instructions. Although trace cache is first introduced to catch the dynamic characteristics of instructions in execution, conventional trace cache (CTC) does increase the power consumption in fetch unit. A Sequential Trace Cache (STC) has been investigated for its power efficiency in this paper.

Original language	English (US)
Article number	999209
Number of pages	1
Journal	Proceedings -Design, Automation and Test in Europe, DATE
DOIs	https://doi.org/10.1109/DATE.2002.999209
State	Published - Dec 1 2002
Event	2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002 - Paris, France Duration: Mar 4 2002 → Mar 8 2002

All Science Journal Classification (ASJC) codes

Engineering(all)

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10.1109/DATE.2002.999209

Cite this

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title = "Power-efficient trace caches",

abstract = "This paper exploits the drawbacks of wasting power when accessing the instruction cache that stores only static sequence of instructions. Although trace cache is first introduced to catch the dynamic characteristics of instructions in execution, conventional trace cache (CTC) does increase the power consumption in fetch unit. A Sequential Trace Cache (STC) has been investigated for its power efficiency in this paper.",

author = "Hu, {J. S.} and N. Vijaykrishnan and A. Kandemir and Irwin, {A. J.}",

year = "2002",

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AU - Vijaykrishnan, N.

AU - Kandemir, A.

AU - Irwin, A. J.

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Y1 - 2002/12/1

N2 - This paper exploits the drawbacks of wasting power when accessing the instruction cache that stores only static sequence of instructions. Although trace cache is first introduced to catch the dynamic characteristics of instructions in execution, conventional trace cache (CTC) does increase the power consumption in fetch unit. A Sequential Trace Cache (STC) has been investigated for its power efficiency in this paper.

AB - This paper exploits the drawbacks of wasting power when accessing the instruction cache that stores only static sequence of instructions. Although trace cache is first introduced to catch the dynamic characteristics of instructions in execution, conventional trace cache (CTC) does increase the power consumption in fetch unit. A Sequential Trace Cache (STC) has been investigated for its power efficiency in this paper.

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DO - 10.1109/DATE.2002.999209

M3 - Conference article

AN - SCOPUS:35048856128

SN - 1530-1591

JO - Proceedings -Design, Automation and Test in Europe, DATE

JF - Proceedings -Design, Automation and Test in Europe, DATE

M1 - 999209

T2 - 2002 Design, Automation and Test in Europe Conference and Exhibition, DATE 2002

Y2 - 4 March 2002 through 8 March 2002

ER -

Power-efficient trace caches

Abstract

All Science Journal Classification (ASJC) codes

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