TY - GEN
T1 - Power integrity/signal integrity co-simulation for fast design closure
AU - Srinivasan, Krishna
AU - Mandrekar, Rohan
AU - Engin, Ege
AU - Swaminathan, Madhavan
PY - 2005
Y1 - 2005
N2 - There is a growing need to reduce the design cycle time of electronic packages to meet the consumer needs quicker. A design methodology to achieve this is to integrate signal and power-delivery analysis. In this paper, a transient simulation technique using S-parameters that does not violate causality is presented. Eye-diagram results are shown, with and without explicit delay extraction. Scalability of this technique has been demonstrated by solving a large sized problem.
AB - There is a growing need to reduce the design cycle time of electronic packages to meet the consumer needs quicker. A design methodology to achieve this is to integrate signal and power-delivery analysis. In this paper, a transient simulation technique using S-parameters that does not violate causality is presented. Eye-diagram results are shown, with and without explicit delay extraction. Scalability of this technique has been demonstrated by solving a large sized problem.
UR - https://www.scopus.com/pages/publications/33847259335
UR - https://www.scopus.com/pages/publications/33847259335#tab=citedBy
M3 - Conference contribution
AN - SCOPUS:33847259335
SN - 0780395786
SN - 9780780395787
T3 - Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005
SP - 49
EP - 53
BT - Proceedings of 7th Electronics Packaging Technology Conference, EPTC 2005
T2 - 7th Electronics Packaging Technology Conference, EPTC 2005
Y2 - 7 December 2005 through 9 December 2005
ER -