TY - JOUR
T1 - Power Side Channel Attack Analysis and Detection
AU - Gattu, Navyata
AU - Imtiaz Khan, Mohammad Nasim
AU - De, Asmit
AU - Ghosh, Swaroop
N1 - Funding Information:
This work is supported by NSF CNS-I722557, CCF-I718474, DGE-1723687 and DGE-1821766, and SRC task 2847.001.
Publisher Copyright:
© 2020 Association on Computer Machinery.
PY - 2020/11/2
Y1 - 2020/11/2
N2 - Side Channel Attack (SCA) is a serious threat to the hardware implementation of cryptographic protocols. Various side channels such as, power, timing, electromagnetic emission and acoustic noise have been explored to extract the secret keys. Machine Learning (ML)-based detection of SCA have been proposed in past which incur high design overheads and, require digitization that reduce their accuracy under process variations. We propose a real-time power SCA detection technique using on-chip sensors based on a thorough analysis. The dependency of phase/frequency of Ring Oscillator (RO) on supply voltage is exploited to detect the insertion of a SCA resistance in the power rail. The proposed approach is validated using simulation with a detailed model of Power Delivery Network (PDN) and power grid. The technique can detect a minimum resistance of 1 \Omega within 2 µs of attack initiation and incurs a tiny fraction of area/power (0.044%/0.1065%, respectively) compared to ML-based techniques.
AB - Side Channel Attack (SCA) is a serious threat to the hardware implementation of cryptographic protocols. Various side channels such as, power, timing, electromagnetic emission and acoustic noise have been explored to extract the secret keys. Machine Learning (ML)-based detection of SCA have been proposed in past which incur high design overheads and, require digitization that reduce their accuracy under process variations. We propose a real-time power SCA detection technique using on-chip sensors based on a thorough analysis. The dependency of phase/frequency of Ring Oscillator (RO) on supply voltage is exploited to detect the insertion of a SCA resistance in the power rail. The proposed approach is validated using simulation with a detailed model of Power Delivery Network (PDN) and power grid. The technique can detect a minimum resistance of 1 \Omega within 2 µs of attack initiation and incurs a tiny fraction of area/power (0.044%/0.1065%, respectively) compared to ML-based techniques.
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U2 - 10.1145/3400302.3415692
DO - 10.1145/3400302.3415692
M3 - Conference article
AN - SCOPUS:85097955635
SN - 1092-3152
VL - 2020-November
JO - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
JF - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
M1 - 9256599
T2 - 39th IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2020
Y2 - 2 November 2020 through 5 November 2020
ER -