TY - JOUR
T1 - Powering Disturb-Free Reconfigurable Computing and Tunable Analog Electronics with Dual-Port Ferroelectric FET
AU - Zhao, Zijian
AU - Deng, Shan
AU - Chatterjee, Swetaki
AU - Jiang, Zhouhang
AU - Islam, Muhammad Shaffatul
AU - Xiao, Yi
AU - Xu, Yixin
AU - Meninger, Scott
AU - Mohamed, Mohamed
AU - Joshi, Rajiv
AU - Chauhan, Yogesh Singh
AU - Mulaosmanovic, Halid
AU - Duenkel, Stefan
AU - Kleimaier, Dominik
AU - Beyer, Sven
AU - Amrouch, Hussam
AU - Narayanan, Vijaykrishnan
AU - Ni, Kai
N1 - Publisher Copyright:
© 2023 American Chemical Society.
PY - 2023
Y1 - 2023
N2 - Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.
AB - Single-port ferroelectric FET (FeFET) that performs write and read operations on the same electrical gate prevents its wide application in tunable analog electronics and suffers from read disturb, especially in the high-threshold voltage (VTH) state as the retention energy barrier is reduced by the applied read bias. To address both issues, we propose to adopt a read disturb-free dual-port FeFET where the write is performed on the gate featuring a ferroelectric layer and the read is done on a separate gate featuring a nonferroelectric dielectric. Combining the unique structure and the separate read gate, read disturb is eliminated as the applied field is aligned with polarization in the high-VTH state, thus improving its stability, while it is screened by the channel inversion charge and exerts no negative impact on the low-VTH state stability. Comprehensive theoretical and experimental validation has been performed on fully depleted silicon-on-insulator (FDSOI) FeFETs integrated on a 22 nm platform, which intrinsically has dual ports with its buried oxide layer acting as the nonferroelectric dielectric. Novel applications that can exploit the proposed dual-port FeFET are proposed and experimentally demonstrated for the first time, including FPGA that harnesses its read disturb-free feature and tunable analog electronics (e.g., frequency tunable ring oscillator in this work) leveraging the separated write and read paths.
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U2 - 10.1021/acsami.3c07827
DO - 10.1021/acsami.3c07827
M3 - Article
C2 - 37962420
AN - SCOPUS:85178500995
SN - 1944-8244
VL - 15
SP - 54602
EP - 54610
JO - ACS Applied Materials and Interfaces
JF - ACS Applied Materials and Interfaces
IS - 47
ER -