TY - JOUR
T1 - Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect
AU - Eachempati, S.
AU - Narayanan, Vijaykrishnan
AU - Nieuwoudt, A.
AU - Massoud, Y.
PY - 2009
Y1 - 2009
N2 - The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54 improvement in area-delay product over the best performing architecture with standard copper interconnect in 22nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43 over FPGAs implemented using traditional copper interconnect in future process technologies.
AB - The authors investigate the performance and reliability of routing architectures in field programmable gate arrays (FPGA) that utilise bundles of single-walled carbon nanotubes (SWCNT) as wires in the FPGA interconnect fabric in future process technologies here. To leverage the performance advantages of nanotube-based interconnect, we explore several important aspects of the FPGA routing architecture including the wire length segmentation distribution and the switch/connection block configurations. The authors also investigate the impact of statistical variations in interconnect properties on FPGA timing yield. The results demonstrate that FPGAs utilising SWCNT bundle interconnect can achieve up to a 54 improvement in area-delay product over the best performing architecture with standard copper interconnect in 22nm process technology. Furthermore, FPGAs implemented using SWCNT-based interconnect can provide a superior performance-yield trade-off of up to 43 over FPGAs implemented using traditional copper interconnect in future process technologies.
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U2 - 10.1049/iet-cds.2008.0149
DO - 10.1049/iet-cds.2008.0149
M3 - Article
AN - SCOPUS:64549151995
SN - 1751-858X
VL - 3
SP - 64
EP - 75
JO - IET Circuits, Devices and Systems
JF - IET Circuits, Devices and Systems
IS - 2
ER -