Abstract
Opto-electronic reconfigurable interconnection networks are limited by significant control latency when used in large multiprocessor systems. This latency is the time required to analyze the current traffic and reconfigure the network to establish the required paths. The goal of latency hiding is to minimize the effect of this control overhead. In this paper, we introduce a technique that performs latency hiding by learning the patterns of communication traffic and using that information to anticipate the need for communication paths. Hence, the network provides the required communication paths before a request for a path is made. In this study, the communication patterns (memory accesses) of a parallel program are used as input to a time delay neural network (TDNN) to perform on-line training and prediction. These predicted communication patterns are used by the interconnection network controller that provides routes for the memory requests. Based on our experiments, the neural network was able to learn highly repetitive communication patterns, and was thus able to predict the allocation of communication paths, resulting in a reduction of communication latency.
Original language | English (US) |
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Title of host publication | International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI), Proceedings |
Editors | Anon |
Publisher | IEEE |
Pages | 326-335 |
Number of pages | 10 |
State | Published - 1995 |
Event | Proceedings of the 2nd International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'95) - San Antonio, TX, USA Duration: Oct 23 1995 → Oct 24 1995 |
Other
Other | Proceedings of the 2nd International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'95) |
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City | San Antonio, TX, USA |
Period | 10/23/95 → 10/24/95 |
All Science Journal Classification (ASJC) codes
- General Computer Science