Predictive precharging for bitline leakage energy reduction

Soontae Kim, N. Vijaykrishnan, M. Kandemir, M. J. Irwin

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations


As technology scales down into deep-submicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit and caches constitute a large portion of the die area. Therefore, there has been much effort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline leakage energy also is critical. Thus, we propose a predictive precharging scheme to reduce bitline leakage energy. Results show that energy savings are significant with little performance degradation. Also, our predictive precharging is more beneficial in more aggressively scaled technologies.

Original languageEnglish (US)
Title of host publicationProceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
EditorsJohn Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages5
ISBN (Electronic)0780374940
StatePublished - 2002
Event15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002Sep 28 2002

Publication series

NameProceedings of the Annual IEEE International ASIC Conference and Exhibit
ISSN (Print)1063-0988


Other15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
Country/TerritoryUnited States

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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