As technology scales down into deep-submicron, leakage energy is becoming a dominant source of energy consumption. Leakage energy is generally proportional to the area of a circuit and caches constitute a large portion of the die area. Therefore, there has been much effort to reduce leakage energy in caches. Most techniques have been targeted at cell leakage energy optimization. Bitline leakage energy also is critical. Thus, we propose a predictive precharging scheme to reduce bitline leakage energy. Results show that energy savings are significant with little performance degradation. Also, our predictive precharging is more beneficial in more aggressively scaled technologies.
|Title of host publication
|Proceedings - 15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
|John Chickanosky, Ram K. Krishnamurthy, P.R. Mukund
|Institute of Electrical and Electronics Engineers Inc.
|Number of pages
|Published - 2002
|15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002 - Rochester, United States
Duration: Sep 25 2002 → Sep 28 2002
|Proceedings of the Annual IEEE International ASIC Conference and Exhibit
|15th Annual IEEE International ASIC/SOC Conference, ASIC/SOC 2002
|9/25/02 → 9/28/02
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering