Process and Technology Drivers for Single Wafer Processes in DRAM Manufacturing

R. A. Weimer, D. C. Powell, P. M. Lenahan

Research output: Chapter in Book/Report/Conference proceedingChapter

2 Scopus citations


This chapter reviews a paper that shows the current status of single wafer Front-End-Of-the-Line (FEOL) processes in Dynamic Random Access Memory (DRAM) production as well as possible paths for current batch processes to move toward single wafer tools. Advanced DRAM processing will migrate toward single-wafer processing only when process requires the advantages of single wafer technologies. Processes such as the oxidations of the word-line poly or active area for gate dielectric formation may become single-wafer processes because of the need for ambient control in the future DRAM devices. Other processes that are post-critical DRAM transistor implants will benefit eventually from the lower thermal budget of the single-wafer processing relative to batch systems. Most processes to date, however, will need to show some distinct process advantage for a single-wafer technology to overcome the Large Cost of Ownership (COO) associated with a single-wafer technology relative to a batch system. COO determines that batch wafer systems dominate the FEOL DRAM processes, such as Low-Pressure Chemical Vapor Deposition (LPCVD) of films, oxidation cycles, and wafer anneal cycles. Process advantage for a single-wafer technology can only be gained by an enabling process that is not available in a batch system.

Original languageEnglish (US)
Title of host publicationRapid Thermal Processing for Future Semiconductor Devices
PublisherElsevier B.V.
Number of pages12
ISBN (Print)9780444513397
StatePublished - Apr 2003

All Science Journal Classification (ASJC) codes

  • General Chemical Engineering


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