Process-Tolerant Low-Power Adaptive Pipeline under Scaled-Vdd

Swaroop Ghosh, Pooja Batra, Keejong Kim, Kaushik Roy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations


Designing low power pipelines in modern high performance microprocessors is becoming a challenging task due to increasing process parameter fluctuation associated with the scaled devices. Conventional low power design techniques typically make the critical paths of pipeline stages sensitive to parametric variations, degrading the yield. We implement a low-power and robust pipeline design methodology which is suitable for aggressive voltage scaling while maintaining high frequency operations. This is achieved by isolating the critical paths; making them predictable (by design) and ensuring they are activated rarely. At scaled supply (with frequency unchanged), any possible delay errors (under 1-cycle operations) are predicted ahead in time and avoided by adaptively stretching the clock period to 2-cycles. The test-chip implementing the design methodology for a two-stage pipeline in 130nm process shows 40% power savings with only 13% performance loss (due to adaptive clock stretching operations) and ∼9.4% area overhead.

Original languageEnglish (US)
Title of host publicationProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007
PublisherInstitute of Electrical and Electronics Engineers Inc.
Number of pages4
ISBN (Electronic)1424407869, 9781424407866
StatePublished - 2007
Event29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007 - San Jose, United States
Duration: Sep 16 2007Sep 19 2007

Publication series

NameProceedings of the IEEE 2007 Custom Integrated Circuits Conference, CICC 2007


Conference29th Annual IEEE Custom Integrated Circuits Conference, CICC 2007
Country/TerritoryUnited States
CitySan Jose

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering


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