Process variation aware parallelization strategies for MPSoCs

Suresh Srinivasan; Raghavan Ramadoss; N. Vijaykrishnan

doi:10.1109/SOCC.2006.283876

Process variation aware parallelization strategies for MPSoCs

Suresh Srinivasan, Raghavan Ramadoss, N. Vijaykrishnan

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

2 Scopus citations

Abstract

Scaling of microprocessors is aggravating the gap between design and manufacturing expectations. Such variations may lead to manufacturing of processors cores with frequencies lower or higher than their expected frequencies. In particular, with the rapid advent of Multiprocessor System on Chips (MPSoC), such manufacturing uncertainties may lead to significant variations in the operating frequencies of different processor cores on the same chip. In this work, we demonstrate that traditional load balanced parallelization schemes need to be revisited to account for such variations. Specifically, we highlight the need for tuning the degree of parallelization and non-uniform workload generation to achieve lower power consumption in next generation MPSoCs.

Original language	English (US)
Title of host publication	2006 IEEE International Systems-on-Chip Conference, SOC
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	179-182
Number of pages	4
ISBN (Print)	0780397819, 9780780397811
DOIs	https://doi.org/10.1109/SOCC.2006.283876
State	Published - Jan 1 2006
Event	2006 IEEE International Systems-on-Chip Conference, SOC - Austin, TX, United States Duration: Sep 24 2006 → Sep 27 2006

Publication series

Name	2006 IEEE International Systems-on-Chip Conference, SOC

Other

Other	2006 IEEE International Systems-on-Chip Conference, SOC
Country/Territory	United States
City	Austin, TX
Period	9/24/06 → 9/27/06

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/SOCC.2006.283876

Cite this

@inproceedings{c07b998c6be746cbb47c8d9441fcf05f,

title = "Process variation aware parallelization strategies for MPSoCs",

abstract = "Scaling of microprocessors is aggravating the gap between design and manufacturing expectations. Such variations may lead to manufacturing of processors cores with frequencies lower or higher than their expected frequencies. In particular, with the rapid advent of Multiprocessor System on Chips (MPSoC), such manufacturing uncertainties may lead to significant variations in the operating frequencies of different processor cores on the same chip. In this work, we demonstrate that traditional load balanced parallelization schemes need to be revisited to account for such variations. Specifically, we highlight the need for tuning the degree of parallelization and non-uniform workload generation to achieve lower power consumption in next generation MPSoCs.",

author = "Suresh Srinivasan and Raghavan Ramadoss and N. Vijaykrishnan",

year = "2006",

month = jan,

day = "1",

doi = "10.1109/SOCC.2006.283876",

language = "English (US)",

isbn = "0780397819",

series = "2006 IEEE International Systems-on-Chip Conference, SOC",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "179--182",

booktitle = "2006 IEEE International Systems-on-Chip Conference, SOC",

address = "United States",

note = "2006 IEEE International Systems-on-Chip Conference, SOC ; Conference date: 24-09-2006 Through 27-09-2006",

}

Srinivasan, S, Ramadoss, R & Vijaykrishnan, N 2006, Process variation aware parallelization strategies for MPSoCs. in 2006 IEEE International Systems-on-Chip Conference, SOC., 4063045, 2006 IEEE International Systems-on-Chip Conference, SOC, Institute of Electrical and Electronics Engineers Inc., pp. 179-182, 2006 IEEE International Systems-on-Chip Conference, SOC, Austin, TX, United States, 9/24/06. https://doi.org/10.1109/SOCC.2006.283876

Process variation aware parallelization strategies for MPSoCs. / Srinivasan, Suresh; Ramadoss, Raghavan; Vijaykrishnan, N.
2006 IEEE International Systems-on-Chip Conference, SOC. Institute of Electrical and Electronics Engineers Inc., 2006. p. 179-182 4063045 (2006 IEEE International Systems-on-Chip Conference, SOC).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

TY - GEN

T1 - Process variation aware parallelization strategies for MPSoCs

AU - Srinivasan, Suresh

AU - Ramadoss, Raghavan

AU - Vijaykrishnan, N.

PY - 2006/1/1

Y1 - 2006/1/1

N2 - Scaling of microprocessors is aggravating the gap between design and manufacturing expectations. Such variations may lead to manufacturing of processors cores with frequencies lower or higher than their expected frequencies. In particular, with the rapid advent of Multiprocessor System on Chips (MPSoC), such manufacturing uncertainties may lead to significant variations in the operating frequencies of different processor cores on the same chip. In this work, we demonstrate that traditional load balanced parallelization schemes need to be revisited to account for such variations. Specifically, we highlight the need for tuning the degree of parallelization and non-uniform workload generation to achieve lower power consumption in next generation MPSoCs.

AB - Scaling of microprocessors is aggravating the gap between design and manufacturing expectations. Such variations may lead to manufacturing of processors cores with frequencies lower or higher than their expected frequencies. In particular, with the rapid advent of Multiprocessor System on Chips (MPSoC), such manufacturing uncertainties may lead to significant variations in the operating frequencies of different processor cores on the same chip. In this work, we demonstrate that traditional load balanced parallelization schemes need to be revisited to account for such variations. Specifically, we highlight the need for tuning the degree of parallelization and non-uniform workload generation to achieve lower power consumption in next generation MPSoCs.

UR - http://www.scopus.com/inward/record.url?scp=43749090216&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=43749090216&partnerID=8YFLogxK

U2 - 10.1109/SOCC.2006.283876

DO - 10.1109/SOCC.2006.283876

M3 - Conference contribution

SN - 0780397819

SN - 9780780397811

T3 - 2006 IEEE International Systems-on-Chip Conference, SOC

SP - 179

EP - 182

BT - 2006 IEEE International Systems-on-Chip Conference, SOC

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2006 IEEE International Systems-on-Chip Conference, SOC

Y2 - 24 September 2006 through 27 September 2006

ER -

Process variation aware parallelization strategies for MPSoCs

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Other

All Science Journal Classification (ASJC) codes

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