Profile-driven energy reduction in network-on-chips

Feihui Li, Guangyu Chen, Mahmut Kandemir, Ibrahim Kolcu

Research output: Contribution to journalArticlepeer-review


Reducing energy consumption of a Network-on-Chip (NoC) is a critical design goal, especially for power-constrained embedded systems. In response, prior research has proposed several circuit/architectural level mechanisms to reduce NoC power consumption. This paper considers the problem from a different perspective and demonstrates that compiler analysis can be very helpful for enhancing the effectiveness of a hardware-based link power management mechanism by increasing the duration of communication links' idle periods. The proposed profile-based approach achieves its goal by maximizing the communication link reuse through compiler-directed, static message re-routing. That is, it clusters the required data communications into a small set of communication links at any given time, which increases the idle periods for the remaining communication links in the network. This helps hardware shut down more communication links and their corresponding buffers to reduce leakage power. The current experimental evaluation, with twelve data-intensive embedded applications, shows that the proposed profile-driven compiler approach reduces leakage energy by more than 35% (on average) as compared to a pure hardware-based link power management scheme.

Original languageEnglish (US)
Pages (from-to)394-404
Number of pages11
JournalACM SIGPLAN Notices
Issue number6
StatePublished - Jun 2007

All Science Journal Classification (ASJC) codes

  • General Computer Science


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