Pseudo-balanced signaling using power transmission lines for parallel I/O links

The performance of a system depends heavily on the communication speed between integrated circuits. Single-ended signaling is widely used for memory interface, but it suffers from simultaneous switching noise, crosstalk, and reference voltage noise. Even with other signaling schemes that remedy the shortcomings of the singled-ended signaling, there still is a limitation in terms of noise reduction due to the power delivery network (PDN). These include techniques such as differential signaling. The disruption between the power and ground planes based on the low target impedance concept induces return path discontinuities during the data transitions, which create displacement current sources between the power and ground planes. These sources induce excessive power supply noise which can only be reduced by increasing the capacitance requirements. The new PDN design proposed in this paper using power transmission lines (PTLs) enables both power and signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed. A modified balanced signaling scheme is applied to PTL, and called as pseudo-balanced PTL (PBPTL). The PBPTL scheme reduces the overhead caused by the conventional balanced signaling scheme and addresses the issues associated with PTL. Extensive simulations and measurements are shown using the PTL approach to demonstrate the enhanced signal integrity as compared to the currently practiced approaches.