Qpace: Power-efficient parallel architecture based on IBM PowerXCell 8i

H. Baier, H. Boettiger, M. Drochner, N. Eicker, U. Fischer, Z. Fodor, A. Frommer, C. Gomez, G. Goldrian, S. Heybrock, D. Hierl, M. Hüsken, T. Huth, B. Krill, J. Lauritsen, T. Lippert, T. Maurer, B. Mendl, N. Meyer, A. NobileI. Ouda, M. Pivanti, D. Pleiter, M. Ries, A. Schäfer, H. Schick, F. Schifano, H. Simma, S. Solbrig, T. Streuer, K. H. Sulanke, R. Tripiccione, J. S. Vogt, T. Wettig, F. Winter

Research output: Contribution to journalArticlepeer-review

18 Scopus citations


QPACE is a novel massively parallel architecture optimized for lattice QCD simulations. Each node comprises an IBM PowerXCell 8i processor. The nodes are interconnected by a custom 3-dimensional torus network implemented on an FPGA. The architecture was systematically optimized with respect to power consumption. This put QPACE in the number one spot on the Green500 List published in November 2009. In this paper we give an overview of the architecture and highlight the steps taken to improve power efficiency.

Original languageEnglish (US)
Pages (from-to)149-154
Number of pages6
JournalComputer Science - Research and Development
Issue number3-4
StatePublished - 2010

All Science Journal Classification (ASJC) codes

  • General Computer Science


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