TY - JOUR
T1 - QPACE
T2 - Quantum chromodynamics parallel computing on the cell broadband engine
AU - Goldrian, Gottfried
AU - Huth, Thomas
AU - Krill, Benjamin
AU - Lauritsen, Jack
AU - Schick, Heiko
AU - Ouda, Ibrahim
AU - Heybrock, Simon
AU - Hierl, Dieter
AU - Maurer, Thilo
AU - Meyer, Nils
AU - Schäfer, Andreas
AU - Solbrig, Stefan
AU - Streuer, Thomas
AU - Wettig, Tilo
AU - Pleiter, Dirk
AU - Sulanke, Karl Heinz
AU - Winter, Frank
AU - Simma, Hubert
AU - Schifano, Sebastiano Fabio
AU - Tripiccione, Raffaele
AU - Nobile, Andrea
AU - Drochner, Matthias
AU - Lippert, Thomas
AU - Fodor, Zoltan
N1 - Funding Information:
QPACE is funded by the Deutsche Forschungsge-meinschaft (DFG) through the SFB/TR-55 frame-work and by IBM. We gratefully acknowledge important contributions to QPACE by Eurotech (Italy) and Knürr (Germany).
PY - 2008/11
Y1 - 2008/11
N2 - Some of the significant issues associated with the development of quantum chromatodynamics parallel computing on the cell broadband engine (QPACE) projects are discussed. The quantum chromatodynamics QPACE projects use a compute node, based on IBM's PowerXCell 8i multicore processor and couples it to a specifically designed network processor in which each node is connected to its nearest neighbors in a 3D toroidal mesh. A Xilinx Virtex-5 field-programmable gate array (FPGA) is used, to facilitate the network processor's implementation. The QPACE project converts the parallel performance into a linear form in the number of nodes. It also enables programmers to divide an algorithm, implemented on a specific architecture into microtasks, which are performed by the model's processing devices.
AB - Some of the significant issues associated with the development of quantum chromatodynamics parallel computing on the cell broadband engine (QPACE) projects are discussed. The quantum chromatodynamics QPACE projects use a compute node, based on IBM's PowerXCell 8i multicore processor and couples it to a specifically designed network processor in which each node is connected to its nearest neighbors in a 3D toroidal mesh. A Xilinx Virtex-5 field-programmable gate array (FPGA) is used, to facilitate the network processor's implementation. The QPACE project converts the parallel performance into a linear form in the number of nodes. It also enables programmers to divide an algorithm, implemented on a specific architecture into microtasks, which are performed by the model's processing devices.
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U2 - 10.1109/MCSE.2008.153
DO - 10.1109/MCSE.2008.153
M3 - Article
AN - SCOPUS:54849404931
SN - 1521-9615
VL - 10
SP - 46
EP - 54
JO - Computing in Science and Engineering
JF - Computing in Science and Engineering
IS - 6
M1 - 4653204
ER -