QsCores: Trading dark silicon for scalable energy efficiency with quasi-specific cores

Ganesh Venkatesh, Jack Sampson, Nathan Goulding-Hotta, Sravanthi Kota Venkata, Michael Bedford Taylor, Steven Swanson

Research output: Chapter in Book/Report/Conference proceedingConference contribution

79 Scopus citations


Transistor density continues to increase exponentially, but power dissipation per transistor is improving only slightly with each generation of Moore's law. Given the constant chip-level power budgets, this exponentially decreases the percentage of transistors that can switch at full frequency with each technology generation. Hence, while the transistor budget continues to increase exponentially, the power budget has become the dominant limiting factor in processor design. In this regime, utilizing transistors to design specialized cores that optimize energy-per-computation becomes an effective approach to improve system performance. To trade transistors for energy efficiency in a scalable manner, we propose Quasi-specific Cores, or QsCores, specialized processors capable of executing multiple general-purpose computations while providing an order of magnitude more energy efficiency than a general-purpose processor. The QsCores design flow is based on the insight that similar code patterns exist within and across applications. Our approach exploits these similar code patterns to ensure that a small set of specialized cores support a large number of commonly used computations. We evaluate QsCores's ability to target both a single application library (e.g., data structures) as well as a diverse workload consisting of applications selected from different domains (e.g., SPECINT, EEMBC, and Vision). Our results show that QsCores can provide 18.4 x better energy efficiency than general-purpose processors while reducing the amount of specialized logic required to support the workload by up to 66%.

Original languageEnglish (US)
Title of host publicationMICRO 44 - Proceedings of the 44th Annual IEEE/ACM Symposium on Microarchitecture
Number of pages12
StatePublished - 2011
Event44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44 - Porto Alegre, RS, Brazil
Duration: Dec 4 2011Dec 7 2011

Publication series

NameProceedings of the Annual International Symposium on Microarchitecture, MICRO
ISSN (Print)1072-4451


Other44th Annual IEEE/ACM Symposium on Microarchitecture, MICRO 44
CityPorto Alegre, RS

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture


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