QuaLITi: Quantum Machine Learning Hardware Selection for Inferencing with Top-Tier Performance

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Quantum Machine Learning (QML) is an accelerating field of study that leverages the principles of quantum mechanics to enhance and innovate within machine learning methodologies. However, Noisy Intermediate-Scale Quantum (NISQ) computers suffer from noise that corrupts the quantum states of the qubits and affects the training and inferencing accuracy. Furthermore, quantum computers have long access queues. A single execution with a pre-defined number of shots can take hours just to reach the top of the wait queue, which is especially disadvantageous to QML algorithms that are iterative in nature. Many vendors provide access to a suite of quantum hardware with varied qubit technologies, number of qubits, cou-pling architectures, and noise characteristics. However, present QML algorithms do not use them for the training procedure and often rely on local noiseless/noisy simulators due to cost and training timing overhead on real hardware. Taking these constraints into account, we perform a study to maximize the inferencing performance of QML workloads based on the choice of hardware selection. Specifically, we perform a detailed analysis of quantum classifiers (both training and inference through the lens of hardware queue wait times) on Iris and reduced Digits datasets under noise and varied conditions such as different hardware and coupling maps. We show that using multiple readily available hardware for training rather than relying on a single hardware, especially if it has a long queue depth of pending jobs, can lead to a performance impact of only 3-4 % while providing up to 45X reduction in training wait time.

Original languageEnglish (US)
Title of host publicationProceedings - 38th International Conference on VLSI Design, VLSID 2025 - held concurrently with 24th International Conference on Embedded Systems, ES 2025
PublisherIEEE Computer Society
Pages296-301
Number of pages6
ISBN (Electronic)9798331522445
DOIs
StatePublished - 2025
Event38th International Conference on VLSI Design, VLSID 2025 - Bengaluru, India
Duration: Jan 4 2025Jan 8 2025

Publication series

NameProceedings of the IEEE International Conference on VLSI Design
ISSN (Print)1063-9667

Conference

Conference38th International Conference on VLSI Design, VLSID 2025
Country/TerritoryIndia
CityBengaluru
Period1/4/251/8/25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

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