Quantifying and optimizing the impact of victim cache line selection in manycore systems

Keyphrases

• Application Performance 20%
• Architectural Level 20%
• Cache Controller 20%
• Cache Hit Ratio 20%
• Cache Line 100%
• Cache Miss 40%
• Cache Replacement 20%
• Core System 20%
• Cycle-accurate Simulation 20%
• Data Locality 20%
• Energy Saving 20%
• Execution Time 20%
• Large Set 20%
• Last-level Cache 80%
• Latency 100%
• Level Scheme 20%
• Line Selection 100%
• Many-core Systems 100%
• Memory Controller 40%
• Memory Writing 20%
• Multithreaded Applications 40%
• Network on chip 60%
• Novel Architectures 20%
• On-chip Memory 20%
• Simulation Infrastructure 20%
• Victim Cache 100%
• Writing Back 80%

Computer Science

• Application Performance 50%
• Architecture Level 50%
• Cache Controller 50%
• Cache Hit Rate 50%
• Data Locality 50%
• Execution Time 50%
• Manycore System 100%
• Memory Controller 100%
• Network Latency 50%
• Networks on Chips 100%
• Oriented Optimization 50%