Abstract
An arithmetic processor based upon a rational representation scheme is examined. The key feature of this rational processor is its ability to efficiently reduce a result ratio to its irreducible form (the greatest common divisor of the numerator and denominator is unity). The reduction algorithm presented generates the reduced ratio in parallel with the evaluation of the ratio's greatest common divisor. Hardware designs for the reduction algorithm and the basic arithmetic operations are given.
| Original language | English (US) |
|---|---|
| Pages | 241-244 |
| Number of pages | 4 |
| State | Published - Jan 1 1981 |
| Event | Proc - Symp on Comput Arith, 5th - Ann Arbor, Mich Duration: May 18 1981 → May 19 1981 |
Other
| Other | Proc - Symp on Comput Arith, 5th |
|---|---|
| City | Ann Arbor, Mich |
| Period | 5/18/81 → 5/19/81 |
All Science Journal Classification (ASJC) codes
- General Engineering