TY - JOUR
T1 - Reconfigurable Ferroelectric Transistor - Part I
T2 - Device Design and Operation
AU - Thirumala, Sandeep Krishna
AU - Gupta, Sumeet Kumar
N1 - Funding Information:
Manuscript received December 4, 2018; revised January 22, 2019; accepted January 29, 2019. Date of publication March 13, 2019; date of current version May 21, 2019. This work was supported by the Defense Advanced Research Projects Agency (DARPA) Young Faculty Award (YFA). The review of this paper was arranged by Editor B. K. Kaushik. (Corresponding author: Sandeep Krishna Thirumala.) The authors are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 USA (e-mail: sthirum@purdue.edu).
Publisher Copyright:
© 2019 IEEE.
PY - 2019/6
Y1 - 2019/6
N2 - In this paper, we propose a novel reconfigurable ferroelectric FET (R-FEFET), which can reconfigure its operation between volatile and nonvolatile modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Employing Landau-Khalatnikov equation-based FEFET model, we extensively analyze the device characteristics in both FinFET and planar technologies. We show that by changing the control voltage between 0 and 1 V, the hysteresis width (HW) can be modulated between 1.1 and 0.3 V. In addition, we show the device characteristics and advantages that R-FEFETs possess to overcome the drawbacks encountered with gate leakage in standard FEFETs. The hold margins in the nonvolatile mode of R-FEFETs increase by ∼10× with respect to standard FEFETs, and the drive current strengths in the volatile mode show 13% improvements when compared to standard FETs. Using the proposed R-FEFETs, we examine a low-power nonvolatile memory design in Part II of this paper.
AB - In this paper, we propose a novel reconfigurable ferroelectric FET (R-FEFET), which can reconfigure its operation between volatile and nonvolatile modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Employing Landau-Khalatnikov equation-based FEFET model, we extensively analyze the device characteristics in both FinFET and planar technologies. We show that by changing the control voltage between 0 and 1 V, the hysteresis width (HW) can be modulated between 1.1 and 0.3 V. In addition, we show the device characteristics and advantages that R-FEFETs possess to overcome the drawbacks encountered with gate leakage in standard FEFETs. The hold margins in the nonvolatile mode of R-FEFETs increase by ∼10× with respect to standard FEFETs, and the drive current strengths in the volatile mode show 13% improvements when compared to standard FETs. Using the proposed R-FEFETs, we examine a low-power nonvolatile memory design in Part II of this paper.
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U2 - 10.1109/TED.2019.2897960
DO - 10.1109/TED.2019.2897960
M3 - Article
AN - SCOPUS:85065873129
SN - 0018-9383
VL - 66
SP - 2771
EP - 2779
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 6
M1 - 8667056
ER -