TY - JOUR
T1 - Reconfigurable ferroelectric transistor-part II
T2 - Application in low-power nonvolatile memories
AU - Thirumala, Sandeep Krishna
AU - Gupta, Sumeet Kumar
N1 - Funding Information:
Manuscript received December 4, 2018; revised January 22, 2019, March 12, 2019, and April 11, 2019; accepted April 17, 2019. Date of current version May 21, 2019. This work was supported by The Defense Advanced Research Projects Agency (DARPA) Young Faculty Award (YFA), under Grant D16AP00109. The review of this paper was arranged by Editor B. K. Kaushik. (Corresponding author: Sandeep Krishna Thirumala.) The authors are with the School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 USA (e-mail: sthirum@purdue.edu).
Publisher Copyright:
© 2019 IEEE.
PY - 2019/6
Y1 - 2019/6
N2 - In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55% lower write power and 37%-72% lower read power at iso access time and 33% lower area compared with a recently proposed standard FEFET-based memory.
AB - In Part I, we proposed reconfigurable ferroelectric transistors (R-FEFETs) with a unique property of dynamic modulation between the volatile (logic) and nonvolatile (memory) modes of operation with the help of a control signal. They showcase excellent robustness in the presence of gate leakage with larger hysteresis in the nonvolatile mode with respect to ferroelectric FETs (FEFETs) and higher ON current in the volatile mode compared with standard FETs. Using the unique attributes of R-FEFETs presented in Part I, we explain the dynamics of transition between various modes of operation for circuit-level applications in this paper. We propose a 3T nonvolatile memory design that offers significant power savings over FEFET-based memories by virtue of the control terminal. Our analysis shows that the proposed R-FEFET memory exhibits 55% lower write power and 37%-72% lower read power at iso access time and 33% lower area compared with a recently proposed standard FEFET-based memory.
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U2 - 10.1109/TED.2019.2912562
DO - 10.1109/TED.2019.2912562
M3 - Article
AN - SCOPUS:85065902925
SN - 0018-9383
VL - 66
SP - 2780
EP - 2788
JO - IEEE Transactions on Electron Devices
JF - IEEE Transactions on Electron Devices
IS - 6
M1 - 8710628
ER -