TY - GEN
T1 - Reducing energy consumption of on-chip networks through a hybrid compiler-runtime approach
AU - Chen, Guangyu
AU - Li, Feihui
AU - Kandemir, Mahmut
PY - 2007
Y1 - 2007
N2 - This paper investigates a compiler-runtime approach for reducing power consumption in the context of the Network-on-Chip (NoC) based chip multiprocessor (CMP) architectures. Our proposed approach is based on the observation that the same communication patterns across the nodes of a mesh based CMP repeat themselves in successive iterations of a loop nest. The approach collects the link usage statistics during the execution of the first few iterations of a given loop nest and computes the slack (allowable delay) for each communication transaction. This information is subsequently utilized in selecting the most appropriate voltage levels for the communication links (and the corresponding frequencies) in executing the remaining iterations of the loop nest. The results with the benchmarks from the MediaBench suite show that, not only this hybrid approach generates better energy savings than a pure hardware-directed voltage scaling scheme, but it also leads to much less performance degradation than the latter. Specifically, the average energy savings achieved by the pure hardware based scheme and our approach are 24.9% and 38.1%, respectively, and the corresponding performance overhead numbers are 8.3% and 2.1%. Our results also show that the hybrid approach generates much better savings than two recently proposed pure compiler based schemes. In addition, our experimental evaluation indicates that the energy savings obtained through the proposed approach are very close to optimal savings (within 3%) under the same performance bound.
AB - This paper investigates a compiler-runtime approach for reducing power consumption in the context of the Network-on-Chip (NoC) based chip multiprocessor (CMP) architectures. Our proposed approach is based on the observation that the same communication patterns across the nodes of a mesh based CMP repeat themselves in successive iterations of a loop nest. The approach collects the link usage statistics during the execution of the first few iterations of a given loop nest and computes the slack (allowable delay) for each communication transaction. This information is subsequently utilized in selecting the most appropriate voltage levels for the communication links (and the corresponding frequencies) in executing the remaining iterations of the loop nest. The results with the benchmarks from the MediaBench suite show that, not only this hybrid approach generates better energy savings than a pure hardware-directed voltage scaling scheme, but it also leads to much less performance degradation than the latter. Specifically, the average energy savings achieved by the pure hardware based scheme and our approach are 24.9% and 38.1%, respectively, and the corresponding performance overhead numbers are 8.3% and 2.1%. Our results also show that the hybrid approach generates much better savings than two recently proposed pure compiler based schemes. In addition, our experimental evaluation indicates that the energy savings obtained through the proposed approach are very close to optimal savings (within 3%) under the same performance bound.
UR - http://www.scopus.com/inward/record.url?scp=47849083756&partnerID=8YFLogxK
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U2 - 10.1109/PACT.2007.4336209
DO - 10.1109/PACT.2007.4336209
M3 - Conference contribution
AN - SCOPUS:47849083756
SN - 0769529445
SN - 9780769529448
T3 - Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT
SP - 163
EP - 174
BT - 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
T2 - 16th International Conference on Parallel Architecture and Compilation Techniques, PACT 2007
Y2 - 15 September 2007 through 19 September 2007
ER -