Reducing Instruction Cache Energy Consumption Using a Compiler-Based Strategy

W. Zhang, J. S. Hu, V. Degalahal, M. Kandemir, N. Vijaykrishnan, M. J. Irwin

Research output: Contribution to journalArticlepeer-review

13 Scopus citations


Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consumed due to leaky memory cells in on-chip caches will constitute a significant portion of the processor's power budget. This work focuses on reducing the leakage energy consumed in the instruction cache using a compiler-directed approach. We present and analyze two compiler-based strategies termed as conservative and optimistic. The conservative approach does not put a cache line into a low leakage mode until it is certain that the current instruction in it is dead. On the other hand, the optimistic approach places a cache line in low leakage mode if it detects that the next access to the instruction will occur only after a long gap.We evaluate different optimization alternatives by combining the compiler strategies with state-preserving and state-destroying leakage control mechanisms.We also evaluate the sensitivity of these optimizations to different high-level compiler transformations, energy parameters, and soft errors.

Original languageEnglish (US)
Pages (from-to)3-33
Number of pages31
JournalACM Transactions on Architecture and Code Optimization
Issue number1
StatePublished - 2004

All Science Journal Classification (ASJC) codes

  • Software
  • Information Systems
  • Hardware and Architecture


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