TY - CHAP

T1 - Regular, area-time efficient carry-lookahead adders

AU - Ngai, Tin Fook

AU - Irwin, Mary Jane

AU - Rawat, Shishpal

N1 - Funding Information:
*This research is supported by AR0 Contract DAAG29-83-K-0126. A preliminary version of this paper appeared in “Proceedings of the Seventh Symposium on Computer Arithmetic,” Urbana, Ill., June 1985.
Funding Information:
This work is supported in part by the Army Research Office under Contract DAAG29-83-K-0126. Thanks go to Poras Balsara for work on the CIF layout plots.

PY - 2015/1/1

Y1 - 2015/1/1

N2 - For fast binary addition, a carry-lookahead (CLA) design is the obvious choice (S. Ong and D. E. Atkins, Proc. Sixth Symposium of Computer Arithmetic, Aarhus, Denmark, June 1983; M. A. Bayoumi, G. A. Jullien, and W. C. Miller, INTEGRATION 1 (1983)). However, the direct implementation of a CLA adder in VLSI faces some undesirable limitations. Either the design lacks regularity, thus increasing the design and implementation costs, or the interconnection wires are too long, thus causing area-time inefficiency and limits on the size of addition. R. P. Brent and H. T. Kung (IEEE Trans. Comput. C-31 (Mar. 1982)) solved the regularity problem by reformulating the carry chain computation. They showed that an n-bit addition can be performed in time O (log n), using area O(n log n) with maximum interconnection wire length O(n). In this paper, we give an alternative log n stage design which is nearly optimum with respect to regularity, area-time efficiency, and maximum interconnection wire length.

AB - For fast binary addition, a carry-lookahead (CLA) design is the obvious choice (S. Ong and D. E. Atkins, Proc. Sixth Symposium of Computer Arithmetic, Aarhus, Denmark, June 1983; M. A. Bayoumi, G. A. Jullien, and W. C. Miller, INTEGRATION 1 (1983)). However, the direct implementation of a CLA adder in VLSI faces some undesirable limitations. Either the design lacks regularity, thus increasing the design and implementation costs, or the interconnection wires are too long, thus causing area-time inefficiency and limits on the size of addition. R. P. Brent and H. T. Kung (IEEE Trans. Comput. C-31 (Mar. 1982)) solved the regularity problem by reformulating the carry chain computation. They showed that an n-bit addition can be performed in time O (log n), using area O(n log n) with maximum interconnection wire length O(n). In this paper, we give an alternative log n stage design which is nearly optimum with respect to regularity, area-time efficiency, and maximum interconnection wire length.

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U2 - 10.1142/9789814641470

DO - 10.1142/9789814641470

M3 - Chapter

AN - SCOPUS:84988654391

SN - 9789814641463

SP - 157

EP - 170

BT - Computer Arithmetic

PB - World Scientific Publishing Co.

ER -